This is a note to let you know that I've just added the patch titled
KVM: x86: Inject #GP on x2APIC WRMSR that sets reserved bits 63:32
to the 6.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
kvm-x86-inject-gp-on-x2apic-wrmsr-that-sets-reserved-bits-63-32.patch
and it can be found in the queue-6.2 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From ab52be1b310bcb39e6745d34a8f0e8475d67381a Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@xxxxxxxxxx>
Date: Sat, 7 Jan 2023 01:10:21 +0000
Subject: KVM: x86: Inject #GP on x2APIC WRMSR that sets reserved bits 63:32
From: Sean Christopherson <seanjc@xxxxxxxxxx>
commit ab52be1b310bcb39e6745d34a8f0e8475d67381a upstream.
Reject attempts to set bits 63:32 for 32-bit x2APIC registers, i.e. all
x2APIC registers except ICR. Per Intel's SDM:
Non-zero writes (by WRMSR instruction) to reserved bits to these
registers will raise a general protection fault exception
Opportunistically fix a typo in a nearby comment.
Reported-by: Marc Orr <marcorr@xxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Reviewed-by: Maxim Levitsky <mlevitsk@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20230107011025.565472-3-seanjc@xxxxxxxxxx
Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/x86/kvm/lapic.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2949,13 +2949,17 @@ static int kvm_lapic_msr_read(struct kvm
static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data)
{
/*
- * ICR is a 64-bit register in x2APIC mode (and Hyper'v PV vAPIC) and
+ * ICR is a 64-bit register in x2APIC mode (and Hyper-V PV vAPIC) and
* can be written as such, all other registers remain accessible only
* through 32-bit reads/writes.
*/
if (reg == APIC_ICR)
return kvm_x2apic_icr_write(apic, data);
+ /* Bits 63:32 are reserved in all other registers. */
+ if (data >> 32)
+ return 1;
+
return kvm_lapic_reg_write(apic, reg, (u32)data);
}
Patches currently in stable-queue which might be from seanjc@xxxxxxxxxx are
queue-6.2/kvm-svm-hyper-v-placate-modpost-section-mismatch-error.patch
queue-6.2/kvm-svm-flush-the-current-tlb-when-activating-avic.patch
queue-6.2/x86-virt-force-gif-1-prior-to-disabling-svm-for-reboot-flows.patch
queue-6.2/kvm-x86-inject-gp-if-wrmsr-sets-reserved-bits-in-apic-self-ipi.patch
queue-6.2/x86-reboot-disable-svm-not-just-vmx-when-stopping-cpus.patch
queue-6.2/kvm-svm-process-icr-on-avic-ipi-delivery-failure-due-to-invalid-target.patch
queue-6.2/kvm-x86-don-t-inhibit-apicv-avic-if-xapic-id-mismatch-is-due-to-32-bit-id.patch
queue-6.2/x86-reboot-disable-virtualization-in-an-emergency-if-svm-is-supported.patch
queue-6.2/kvm-svm-don-t-put-load-avic-when-setting-virtual-apic-mode.patch
queue-6.2/x86-crash-disable-virt-in-core-nmi-crash-handler-to-avoid-double-shootdown.patch
queue-6.2/kvm-register-dev-kvm-as-the-_very_-last-thing-during-initialization.patch
queue-6.2/kvm-x86-don-t-inhibit-apicv-avic-on-xapic-id-change-if-apic-is-disabled.patch
queue-6.2/kvm-destroy-target-device-if-coalesced-mmio-unregistration-fails.patch
queue-6.2/kvm-svm-fix-potential-overflow-in-sev-s-send-receive_update_data.patch
queue-6.2/kvm-x86-blindly-get-current-x2apic-reg-value-on-nodecode-write-traps.patch
queue-6.2/kvm-x86-purge-highest-isr-cache-when-updating-apicv-state.patch
queue-6.2/kvm-x86-inject-gp-on-x2apic-wrmsr-that-sets-reserved-bits-63-32.patch
queue-6.2/kvm-vmx-fix-crash-due-to-uninitialized-current_vmcs.patch
