This is a note to let you know that I've just added the patch titled
KVM: x86: Purge "highest ISR" cache when updating APICv state
to the 6.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
kvm-x86-purge-highest-isr-cache-when-updating-apicv-state.patch
and it can be found in the queue-6.2 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 97a71c444a147ae41c7d0ab5b3d855d7f762f3ed Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@xxxxxxxxxx>
Date: Fri, 6 Jan 2023 01:12:35 +0000
Subject: KVM: x86: Purge "highest ISR" cache when updating APICv state
From: Sean Christopherson <seanjc@xxxxxxxxxx>
commit 97a71c444a147ae41c7d0ab5b3d855d7f762f3ed upstream.
Purge the "highest ISR" cache when updating APICv state on a vCPU. The
cache must not be used when APICv is active as hardware may emulate EOIs
(and other operations) without exiting to KVM.
This fixes a bug where KVM will effectively block IRQs in perpetuity due
to the "highest ISR" never getting reset if APICv is activated on a vCPU
while an IRQ is in-service. Hardware emulates the EOI and KVM never gets
a chance to update its cache.
Fixes: b26a695a1d78 ("kvm: lapic: Introduce APICv update helper function")
Cc: stable@xxxxxxxxxxxxxxx
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
Cc: Maxim Levitsky <mlevitsk@xxxxxxxxxx>
Reviewed-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
Reviewed-by: Maxim Levitsky <mlevitsk@xxxxxxxxxx>
Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
Message-Id: <20230106011306.85230-3-seanjc@xxxxxxxxxx>
Signed-off-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/x86/kvm/lapic.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2429,6 +2429,7 @@ void kvm_apic_update_apicv(struct kvm_vc
*/
apic->isr_count = count_vectors(apic->regs + APIC_ISR);
}
+ apic->highest_isr_cache = -1;
}
void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
@@ -2484,7 +2485,6 @@ void kvm_lapic_reset(struct kvm_vcpu *vc
kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
}
kvm_apic_update_apicv(vcpu);
- apic->highest_isr_cache = -1;
update_divide_count(apic);
atomic_set(&apic->lapic_timer.pending, 0);
@@ -2772,7 +2772,6 @@ int kvm_apic_set_state(struct kvm_vcpu *
__start_apic_timer(apic, APIC_TMCCT);
kvm_lapic_set_reg(apic, APIC_TMCCT, 0);
kvm_apic_update_apicv(vcpu);
- apic->highest_isr_cache = -1;
if (apic->apicv_active) {
static_call_cond(kvm_x86_apicv_post_state_restore)(vcpu);
static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, apic_find_highest_irr(apic));
Patches currently in stable-queue which might be from seanjc@xxxxxxxxxx are
queue-6.2/kvm-svm-hyper-v-placate-modpost-section-mismatch-error.patch
queue-6.2/kvm-svm-flush-the-current-tlb-when-activating-avic.patch
queue-6.2/x86-virt-force-gif-1-prior-to-disabling-svm-for-reboot-flows.patch
queue-6.2/kvm-x86-inject-gp-if-wrmsr-sets-reserved-bits-in-apic-self-ipi.patch
queue-6.2/x86-reboot-disable-svm-not-just-vmx-when-stopping-cpus.patch
queue-6.2/kvm-svm-process-icr-on-avic-ipi-delivery-failure-due-to-invalid-target.patch
queue-6.2/kvm-x86-don-t-inhibit-apicv-avic-if-xapic-id-mismatch-is-due-to-32-bit-id.patch
queue-6.2/x86-reboot-disable-virtualization-in-an-emergency-if-svm-is-supported.patch
queue-6.2/kvm-svm-don-t-put-load-avic-when-setting-virtual-apic-mode.patch
queue-6.2/x86-crash-disable-virt-in-core-nmi-crash-handler-to-avoid-double-shootdown.patch
queue-6.2/kvm-register-dev-kvm-as-the-_very_-last-thing-during-initialization.patch
queue-6.2/kvm-x86-don-t-inhibit-apicv-avic-on-xapic-id-change-if-apic-is-disabled.patch
queue-6.2/kvm-destroy-target-device-if-coalesced-mmio-unregistration-fails.patch
queue-6.2/kvm-svm-fix-potential-overflow-in-sev-s-send-receive_update_data.patch
queue-6.2/kvm-x86-blindly-get-current-x2apic-reg-value-on-nodecode-write-traps.patch
queue-6.2/kvm-x86-purge-highest-isr-cache-when-updating-apicv-state.patch
queue-6.2/kvm-x86-inject-gp-on-x2apic-wrmsr-that-sets-reserved-bits-63-32.patch
queue-6.2/kvm-vmx-fix-crash-due-to-uninitialized-current_vmcs.patch
