This is a note to let you know that I've just added the patch titled
KVM: SVM: Flush the "current" TLB when activating AVIC
to the 6.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
kvm-svm-flush-the-current-tlb-when-activating-avic.patch
and it can be found in the queue-6.2 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 0ccf3e7cb95a2db8ddb2a44812037ffba8166dc9 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@xxxxxxxxxx>
Date: Fri, 6 Jan 2023 01:12:36 +0000
Subject: KVM: SVM: Flush the "current" TLB when activating AVIC
From: Sean Christopherson <seanjc@xxxxxxxxxx>
commit 0ccf3e7cb95a2db8ddb2a44812037ffba8166dc9 upstream.
Flush the TLB when activating AVIC as the CPU can insert into the TLB
while AVIC is "locally" disabled. KVM doesn't treat "APIC hardware
disabled" as VM-wide AVIC inhibition, and so when a vCPU has its APIC
hardware disabled, AVIC is not guaranteed to be inhibited. As a result,
KVM may create a valid NPT mapping for the APIC base, which the CPU can
cache as a non-AVIC translation.
Note, Intel handles this in vmx_set_virtual_apic_mode().
Reviewed-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
Reviewed-by: Maxim Levitsky <mlevitsk@xxxxxxxxxx>
Message-Id: <20230106011306.85230-4-seanjc@xxxxxxxxxx>
Signed-off-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/x86/kvm/svm/avic.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/x86/kvm/svm/avic.c
+++ b/arch/x86/kvm/svm/avic.c
@@ -86,6 +86,12 @@ static void avic_activate_vmcb(struct vc
/* Disabling MSR intercept for x2APIC registers */
svm_set_x2apic_msr_interception(svm, false);
} else {
+ /*
+ * Flush the TLB, the guest may have inserted a non-APIC
+ * mapping into the TLB while AVIC was disabled.
+ */
+ kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, &svm->vcpu);
+
/* For xAVIC and hybrid-xAVIC modes */
vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID;
/* Enabling MSR intercept for x2APIC registers */
Patches currently in stable-queue which might be from seanjc@xxxxxxxxxx are
queue-6.2/kvm-svm-hyper-v-placate-modpost-section-mismatch-error.patch
queue-6.2/kvm-svm-flush-the-current-tlb-when-activating-avic.patch
queue-6.2/x86-virt-force-gif-1-prior-to-disabling-svm-for-reboot-flows.patch
queue-6.2/kvm-x86-inject-gp-if-wrmsr-sets-reserved-bits-in-apic-self-ipi.patch
queue-6.2/x86-reboot-disable-svm-not-just-vmx-when-stopping-cpus.patch
queue-6.2/kvm-svm-process-icr-on-avic-ipi-delivery-failure-due-to-invalid-target.patch
queue-6.2/kvm-x86-don-t-inhibit-apicv-avic-if-xapic-id-mismatch-is-due-to-32-bit-id.patch
queue-6.2/x86-reboot-disable-virtualization-in-an-emergency-if-svm-is-supported.patch
queue-6.2/kvm-svm-don-t-put-load-avic-when-setting-virtual-apic-mode.patch
queue-6.2/x86-crash-disable-virt-in-core-nmi-crash-handler-to-avoid-double-shootdown.patch
queue-6.2/kvm-register-dev-kvm-as-the-_very_-last-thing-during-initialization.patch
queue-6.2/kvm-x86-don-t-inhibit-apicv-avic-on-xapic-id-change-if-apic-is-disabled.patch
queue-6.2/kvm-destroy-target-device-if-coalesced-mmio-unregistration-fails.patch
queue-6.2/kvm-svm-fix-potential-overflow-in-sev-s-send-receive_update_data.patch
queue-6.2/kvm-x86-blindly-get-current-x2apic-reg-value-on-nodecode-write-traps.patch
queue-6.2/kvm-x86-purge-highest-isr-cache-when-updating-apicv-state.patch
queue-6.2/kvm-x86-inject-gp-on-x2apic-wrmsr-that-sets-reserved-bits-63-32.patch
queue-6.2/kvm-vmx-fix-crash-due-to-uninitialized-current_vmcs.patch
