Patch "arm64: dts: qcom: ipq8074: correct PCIe QMP PHY output clock names" has been added to the 5.10-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    arm64: dts: qcom: ipq8074: correct PCIe QMP PHY output clock names

to the 5.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-dts-qcom-ipq8074-correct-pcie-qmp-phy-output-c.patch
and it can be found in the queue-5.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit f62e49c178272e2efdf4c5a3ed84c6bd708801bd
Author: Robert Marko <robimarko@xxxxxxxxx>
Date:   Fri Jan 13 17:44:49 2023 +0100

    arm64: dts: qcom: ipq8074: correct PCIe QMP PHY output clock names
    
    [ Upstream commit 0e8b90c0256cf9c9589e2cee517dedc987a34355 ]
    
    Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix
    IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC
    driver is relying on the old names to match them as they are being used as
    the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk.
    
    This broke parenting as GCC could not find the parent clock, so fix it by
    changing to the names that driver is expecting.
    
    Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
    Signed-off-by: Robert Marko <robimarko@xxxxxxxxx>
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20230113164449.906002-9-robimarko@xxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 4ef364c010125..25f78c71e0105 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -192,7 +192,7 @@ pcie_phy0: phy@84200 {
 				#clock-cells = <0>;
 				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 				clock-names = "pipe0";
-				clock-output-names = "pcie_0_pipe_clk";
+				clock-output-names = "pcie20_phy0_pipe_clk";
 			};
 		};
 
@@ -220,7 +220,7 @@ pcie_phy1: phy@8e200 {
 				#clock-cells = <0>;
 				clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
 				clock-names = "pipe0";
-				clock-output-names = "pcie_1_pipe_clk";
+				clock-output-names = "pcie20_phy1_pipe_clk";
 			};
 		};