Patch "drm/amd/display: fix FCLK pstate change underflow" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/amd/display: fix FCLK pstate change underflow

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-fix-fclk-pstate-change-underflow.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 4dc21b911ea2d401734843a2c8eebaa290d5a25d
Author: Vladimir Stempen <vladimir.stempen@xxxxxxx>
Date:   Tue Jan 17 14:14:42 2023 -0500

    drm/amd/display: fix FCLK pstate change underflow
    
    [ Upstream commit 972243f973eb0821084e5833d5f7f4ed025f42da ]
    
    [Why]
    Currently we set FCLK p-state change
    watermark calculated based on dummy
    p-state latency when UCLK p-state is
    not supported
    
    [How]
    Calculate FCLK p-state change watermark
    based on on FCLK pstate change latency
    in case UCLK p-state is not supported
    
    Reviewed-by: Nevenko Stupar <Nevenko.Stupar@xxxxxxx>
    Acked-by: Alex Hung <alex.hung@xxxxxxx>
    Signed-off-by: Vladimir Stempen <vladimir.stempen@xxxxxxx>
    Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index d90216d2fe3a8..04cc96e700981 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1963,6 +1963,10 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
 		 */
 		context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
+		/* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case
+		 * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported
+		 */
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	} else {
 		/* Set A:
 		 * All clocks min.



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