Patch "drm/vc4: hdmi: Correct interlaced timings again" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/vc4: hdmi: Correct interlaced timings again

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-vc4-hdmi-correct-interlaced-timings-again.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 61b8d461b7de69707ca4b85627b0482fa07df0d5
Author: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>
Date:   Wed Dec 7 12:53:25 2022 +0100

    drm/vc4: hdmi: Correct interlaced timings again
    
    [ Upstream commit 771d6539f27bd55f43d8a95d53a7eeaaffa2681c ]
    
    The back porch timings were correct, only the sync offset was wrong.
    Correct timing is now reported for 1080i and 576i, but the h offset is
    incorrect for 480i for non-obvious reasons.
    
    Fixes: fb10dc451c0f ("drm/vc4: hdmi: Correct HDMI timing registers for interlaced modes")
    Signed-off-by: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20221207-rpi-hvs-crtc-misc-v1-14-1f8e0770798b@xxxxxxxxxx
    Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 0d0b6df4df153..ea2eaf6032caa 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1306,11 +1306,12 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 	u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
 				   VC5_HDMI_VERTB_VSPO) |
-		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
+		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
+				   interlaced,
 				   VC4_HDMI_VERTB_VBP));
 	u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 			  VC4_SET_FIELD(mode->crtc_vtotal -
-					mode->crtc_vsync_end - interlaced,
+					mode->crtc_vsync_end,
 					VC4_HDMI_VERTB_VBP));
 	unsigned long flags;
 	unsigned char gcp;



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