Patch "drm/amd/display: Reset DMUB mailbox SW state after HW reset" has been added to the 6.1-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    drm/amd/display: Reset DMUB mailbox SW state after HW reset

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-reset-dmub-mailbox-sw-state-after-hw.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 1b44d9fd71360e62a035fac7877c7a2471a119e9
Author: Nicholas Kazlauskas <nicholas.kazlauskas@xxxxxxx>
Date:   Fri Jan 20 11:14:30 2023 -0500

    drm/amd/display: Reset DMUB mailbox SW state after HW reset
    
    [ Upstream commit 154711aa5759ef9b45903124fa813c4c29ee681c ]
    
    [Why]
    Otherwise we can be out of sync with what's in the hardware, leading
    to us rerunning every command that's presently in the ringbuffer.
    
    [How]
    Reset software state for the mailboxes in hw_reset callback.
    This is already done as part of the mailbox init in hw_init, but we
    do need to remember to reset the last cached wptr value as well here.
    
    Reviewed-by: Hansen Dsouza <hansen.dsouza@xxxxxxx>
    Acked-by: Alex Hung <alex.hung@xxxxxxx>
    Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@xxxxxxx>
    Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 4a122925c3ae9..92c18bfb98b3b 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -532,6 +532,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 	if (dmub->hw_funcs.reset)
 		dmub->hw_funcs.reset(dmub);
 
+	/* reset the cache of the last wptr as well now that hw is reset */
+	dmub->inbox1_last_wptr = 0;
+
 	cw0.offset.quad_part = inst_fb->gpu_addr;
 	cw0.region.base = DMUB_CW0_BASE;
 	cw0.region.top = cw0.region.base + inst_fb->size - 1;
@@ -649,6 +652,15 @@ enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
 	if (dmub->hw_funcs.reset)
 		dmub->hw_funcs.reset(dmub);
 
+	/* mailboxes have been reset in hw, so reset the sw state as well */
+	dmub->inbox1_last_wptr = 0;
+	dmub->inbox1_rb.wrpt = 0;
+	dmub->inbox1_rb.rptr = 0;
+	dmub->outbox0_rb.wrpt = 0;
+	dmub->outbox0_rb.rptr = 0;
+	dmub->outbox1_rb.wrpt = 0;
+	dmub->outbox1_rb.rptr = 0;
+
 	dmub->hw_init = false;
 
 	return DMUB_STATUS_OK;