This is a note to let you know that I've just added the patch titled dt-bindings: riscv: fix underscore requirement for multi-letter extensions to the 6.1-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: dt-bindings-riscv-fix-underscore-requirement-for-multi-letter-extensions.patch and it can be found in the queue-6.1 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From ec64efc4966edf19fa1bc398a26bddfbadc1605f Mon Sep 17 00:00:00 2001 From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Date: Mon, 5 Dec 2022 17:44:59 +0000 Subject: dt-bindings: riscv: fix underscore requirement for multi-letter extensions From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> commit ec64efc4966edf19fa1bc398a26bddfbadc1605f upstream. The RISC-V ISA Manual allows the first multi-letter extension to avoid a leading underscore. Underscores are only required between multi-letter extensions. The dt-binding does not validate that a multi-letter extension is canonically ordered, as that'd need an even worse regex than is here, but it should not fail validation for valid ISA strings. Allow the first multi-letter extension to appear immediately after the single-letter extensions. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5 Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators") Acked-by: Guo Ren <guoren@xxxxxxxxxx> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Acked-by: Rob Herring <robh@xxxxxxxxxx> Reviewed-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> Acked-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> Link: https://lore.kernel.org/r/20221205174459.60195-2-conor@xxxxxxxxxx Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 90a7cabf58fe..97659bb71811 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false -- 2.39.1 Patches currently in stable-queue which might be from conor.dooley@xxxxxxxxxxxxx are queue-6.1/dt-bindings-riscv-fix-underscore-requirement-for-multi-letter-extensions.patch queue-6.1/riscv-move-call-to-init_cpu_topology-to-later-initia.patch queue-6.1/dt-bindings-riscv-fix-single-letter-canonical-order.patch