Patch "arm64: dts: imx8mm-beacon: Fix ecspi2 pinmux" has been added to the 5.10-stable tree

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This is a note to let you know that I've just added the patch titled

    arm64: dts: imx8mm-beacon: Fix ecspi2 pinmux

to the 5.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-dts-imx8mm-beacon-fix-ecspi2-pinmux.patch
and it can be found in the queue-5.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 1a3b4a99d51770c8d19d9adebeb1d2cf281fbb31
Author: Adam Ford <aford173@xxxxxxxxx>
Date:   Fri Dec 2 13:10:37 2022 -0600

    arm64: dts: imx8mm-beacon: Fix ecspi2 pinmux
    
    [ Upstream commit 5225ba9db112ec4ed67da5e4d8b72e618573955e ]
    
    Early hardware did not support hardware handshaking on the UART, but
    final production hardware did.  When the hardware was updated the chip
    select was changed to facilitate hardware handshaking on UART3.  Fix the
    ecspi2 pin mux to eliminate a pin conflict with UART3 and allow the
    EEPROM to operate again.
    
    Fixes: 4ce01ce36d77 ("arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3")
    Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
    Signed-off-by: Shawn Guo <shawnguo@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
index 5667009aae13..674a0ab8a539 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
@@ -70,7 +70,7 @@ sound {
 &ecspi2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_espi2>;
-	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
 	eeprom@0 {
@@ -187,7 +187,7 @@ pinctrl_espi2: espi2grp {
 			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
 			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
 			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
-			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x41
+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x41
 		>;
 	};
 



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