This is a note to let you know that I've just added the patch titled
drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-amdgpu-pm-use-the-specific-mailbox-registers-only-for-smu-ip-v13.0.4.patch
and it can be found in the queue-6.1 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 069a5af97ce3a1448a3566ce8b63b60e51e19958 Mon Sep 17 00:00:00 2001
From: Tim Huang <tim.huang@xxxxxxx>
Date: Mon, 24 Oct 2022 11:05:59 +0800
Subject: drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4
From: Tim Huang <tim.huang@xxxxxxx>
commit 069a5af97ce3a1448a3566ce8b63b60e51e19958 upstream.
The SMU IP v13.0.4 ppt interface is shared by IP v13.0.11, they use
the different mailbox register offset. So use the specific mailbox
registers offset for v13.0.4.
Signed-off-by: Tim Huang <tim.huang@xxxxxxx>
Signed-off-by: Yifan Zhang <yifan1.zhang@xxxxxxx>
Reviewed-by: Aaron Liu <aaron.liu@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Cc: "Limonciello, Mario" <Mario.Limonciello@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -1026,6 +1026,15 @@ static const struct pptable_funcs smu_v1
.set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu,
};
+static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+}
+
void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
@@ -1035,7 +1044,9 @@ void smu_v13_0_4_set_ppt_funcs(struct sm
smu->feature_map = smu_v13_0_4_feature_mask_map;
smu->table_map = smu_v13_0_4_table_map;
smu->is_apu = true;
- smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
- smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
- smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
+ smu_v13_0_4_set_smu_mailbox_registers(smu);
+ else
+ smu_v13_0_set_smu_mailbox_registers(smu);
}
Patches currently in stable-queue which might be from tim.huang@xxxxxxx are
queue-6.1/drm-amdgpu-discovery-add-psp-ip-v13.0.11-support.patch
queue-6.1/drm-amdgpu-enable-gfx-clock-gating-control-for-gc-ip-v11.0.4.patch
queue-6.1/drm-amdgpu-enable-psp-ip-v13.0.11-support.patch
queue-6.1/drm-amdgpu-enable-gfx-ip-v11.0.4-cg-support.patch
queue-6.1/drm-amdgpu-enable-gfx-power-gating-for-gc-ip-v11.0.4.patch
queue-6.1/drm-amdgpu-soc21-add-mode2-asic-reset-for-smu-ip-v13.0.11.patch
queue-6.1/drm-amdgpu-add-tmz-support-for-gc-ip-v11.0.4.patch
queue-6.1/drm-amdgpu-pm-use-the-specific-mailbox-registers-only-for-smu-ip-v13.0.4.patch
