Patch "drm/msm/a6xx: Fix speed-bin detection vs probe-defer" has been added to the 5.15-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    drm/msm/a6xx: Fix speed-bin detection vs probe-defer

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-msm-a6xx-fix-speed-bin-detection-vs-probe-defer.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 8513f7d125658bc95881967dc41338646d170e51
Author: Rob Clark <robdclark@xxxxxxxxxxxx>
Date:   Tue Nov 15 07:46:34 2022 -0800

    drm/msm/a6xx: Fix speed-bin detection vs probe-defer
    
    [ Upstream commit f6d1918794ef92b4e26b80c3d40365347b76b1fd ]
    
    If we get an error (other than -ENOENT) we need to propagate that up the
    stack.  Otherwise if the nvmem driver hasn't probed yet, we'll end up
    end up claiming that we support all the OPPs which is not likely to be
    true (and on some generations impossible to be true, ie. if there are
    conflicting OPPs).
    
    v2: Update commit msg, gc unused label, etc
    v3: Add previously missing \n's
    
    Fixes: fe7952c629da ("drm/msm: Add speed-bin support to a618 gpu")
    Signed-off-by: Rob Clark <robdclark@xxxxxxxxxxxx>
    Reviewed-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
    Reviewed-by: Akhil P Oommen <quic_akhilpo@xxxxxxxxxxx>
    Patchwork: https://patchwork.freedesktop.org/patch/511690/
    Link: https://lore.kernel.org/r/20221115154637.1613968-1-robdclark@xxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index c0dec5b919d4..2d07c02c59f1 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1746,7 +1746,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
 
 	if (val == UINT_MAX) {
 		DRM_DEV_ERROR(dev,
-			"missing support for speed-bin: %u. Some OPPs may not be supported by hardware",
+			"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
 			fuse);
 		return UINT_MAX;
 	}
@@ -1756,7 +1756,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
 
 static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
 {
-	u32 supp_hw = UINT_MAX;
+	u32 supp_hw;
 	u32 speedbin;
 	int ret;
 
@@ -1768,15 +1768,13 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
 	if (ret == -ENOENT) {
 		return 0;
 	} else if (ret) {
-		DRM_DEV_ERROR(dev,
-			      "failed to read speed-bin (%d). Some OPPs may not be supported by hardware",
-			      ret);
-		goto done;
+		dev_err_probe(dev, ret,
+			      "failed to read speed-bin. Some OPPs may not be supported by hardware\n");
+		return ret;
 	}
 
 	supp_hw = fuse_to_supp_hw(dev, rev, speedbin);
 
-done:
 	ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
 	if (ret)
 		return ret;