Patch "drm/amd/display: Fix DTBCLK disable requests and SRC_SEL programming" has been added to the 6.0-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    drm/amd/display: Fix DTBCLK disable requests and SRC_SEL programming

to the 6.0-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-fix-dtbclk-disable-requests-and-src_.patch
and it can be found in the queue-6.0 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 56aacff0b50b8d8595f967d37a6c7c264f8cc6b7
Author: Alvin Lee <Alvin.Lee2@xxxxxxx>
Date:   Sat Nov 19 11:42:41 2022 -0500

    drm/amd/display: Fix DTBCLK disable requests and SRC_SEL programming
    
    [ Upstream commit f6015da7f2410109bd2ccd2e2828f26185aeb81d ]
    
    [Description]
    - When transitioning FRL / DP2 is not required, we will always request
      DTBCLK = 0Mhz, but PMFW returns the min freq
    - This causes us to make DTBCLK requests every time we call optimize
      after transitioning from FRL to non-FRL
    - If DTBCLK is not required, request the min instead (then we only need
      to make 1 extra request at boot time)
    - Also when programming PIPE_DTO_SRC_SEL, don't programming for DP
      first, just programming once for the required selection (programming
      DP on an HDMI connection then switching back causes corruption)
    
    Reviewed-by: Dillon Varone <Dillon.Varone@xxxxxxx>
    Acked-by: Jasdeep Dhillon <jdhillon@xxxxxxx>
    Signed-off-by: Alvin Lee <Alvin.Lee2@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index e7f1d5f8166f..59a29c32f66a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -436,7 +436,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 	}
 
 	if (!new_clocks->dtbclk_en) {
-		new_clocks->ref_dtbclk_khz = 0;
+		new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
 	}
 
 	/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index 6dd8dadd68a5..6f160f65c8fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -225,11 +225,7 @@ void dccg32_set_dtbclk_dto(
 	} else {
 		REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
 				DTBCLK_DTO_ENABLE[params->otg_inst], 0,
-				PIPE_DTO_SRC_SEL[params->otg_inst], 1);
-		if (params->is_hdmi)
-			REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
-				PIPE_DTO_SRC_SEL[params->otg_inst], 0);
-
+				PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1);
 		REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
 		REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
 	}