Patch "drm/amd/display: Fix display corruption w/ VSR enable" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/amd/display: Fix display corruption w/ VSR enable

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-fix-display-corruption-w-vsr-enable.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 0a7f7e667b6214b0f7acef59715c35c367c019e7
Author: Ilya Bakoulin <Ilya.Bakoulin@xxxxxxx>
Date:   Fri Nov 11 12:03:54 2022 -0500

    drm/amd/display: Fix display corruption w/ VSR enable
    
    [ Upstream commit e643cd384270fd3a4b66f65f15dafc8db0607adc ]
    
    [Why]
    Brief corruption is observed on hotplug/unplug with certain display
    configurations when VSR is enabled.
    
    [How]
    Work around the issue by avoiding 2to1 ODM when stream plane_count is 0.
    
    Reviewed-by: Dillon Varone <Dillon.Varone@xxxxxxx>
    Acked-by: Brian Chang <Brian.Chang@xxxxxxx>
    Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@xxxxxxx>
    Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index d1598e3131f6..33ab6fdc3617 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1901,7 +1901,7 @@ int dcn32_populate_dml_pipes_from_context(
 
 		pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
 		if (context->stream_count == 1 &&
-				context->stream_status[0].plane_count <= 1 &&
+				context->stream_status[0].plane_count == 1 &&
 				!dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) &&
 				is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) &&
 				pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ &&



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