This is a note to let you know that I've just added the patch titled drm/msm/dsi: Prevent signed BPG offsets from bleeding into adjacent bits to the 6.1-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: drm-msm-dsi-prevent-signed-bpg-offsets-from-bleeding.patch and it can be found in the queue-6.1 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. commit 7d7a92fea3da5964d6efcb7c89c0294cdeeda739 Author: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> Date: Wed Oct 26 20:28:24 2022 +0200 drm/msm/dsi: Prevent signed BPG offsets from bleeding into adjacent bits [ Upstream commit cc84b66be223d36a3d10d59d68ba647e72db3099 ] The bpg_offset array contains negative BPG offsets which fill the full 8 bits of a char thanks to two's complement: this however results in those bits bleeding into the next field when the value is packed into DSC PPS by the drm_dsc_helper function, which only expects range_bpg_offset to contain 6-bit wide values. As a consequence random slices appear corrupted on-screen (tested on a Sony Tama Akatsuki device with sdm845). Use AND operators to limit these two's complement values to 6 bits, similar to the AMD and i915 drivers. Fixes: b9080324d6ca ("drm/msm/dsi: add support for dsc data") Reviewed-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> Patchwork: https://patchwork.freedesktop.org/patch/508941/ Link: https://lore.kernel.org/r/20221026182824.876933-11-marijn.suijten@xxxxxxxxxxxxxx Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index c229cf6eeb9c..89aadd3b3202 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1782,7 +1782,11 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { dsc->rc_range_params[i].range_min_qp = min_qp[i]; dsc->rc_range_params[i].range_max_qp = max_qp[i]; - dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i]; + /* + * Range BPG Offset contains two's-complement signed values that fill + * 8 bits, yet the registers and DCS PPS field are only 6 bits wide. + */ + dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK; } dsc->initial_offset = 6144; /* Not bpp 12 */