This is a note to let you know that I've just added the patch titled
dmaengine: at_hdmac: Don't allow CPU to reorder channel enable
to the 6.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
dmaengine-at_hdmac-don-t-allow-cpu-to-reorder-channel-enable.patch
and it can be found in the queue-6.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 580ee84405c27d6ed419abe4d2b3de1968abdafd Mon Sep 17 00:00:00 2001
From: Tudor Ambarus <tudor.ambarus@xxxxxxxxxxxxx>
Date: Tue, 25 Oct 2022 12:02:47 +0300
Subject: dmaengine: at_hdmac: Don't allow CPU to reorder channel enable
From: Tudor Ambarus <tudor.ambarus@xxxxxxxxxxxxx>
commit 580ee84405c27d6ed419abe4d2b3de1968abdafd upstream.
at_hdmac uses __raw_writel for register writes. In the absence of a
barrier, the CPU may reorder the register operations.
Introduce a write memory barrier so that the CPU does not reorder the
channel enable, thus the start of the transfer, without making sure that
all the pre-required register fields are already written.
Fixes: dc78baa2b90b ("dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller")
Reported-by: Peter Rosin <peda@xxxxxxxxxx>
Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Link: https://lore.kernel.org/lkml/13c6c9a2-6db5-c3bf-349b-4c127ad3496a@xxxxxxxxxx/
Acked-by: Nicolas Ferre <nicolas.ferre@xxxxxxxxxxxxx>
Link: https://lore.kernel.org/r/20221025090306.297886-1-tudor.ambarus@xxxxxxxxxxxxx
Link: https://lore.kernel.org/r/20221025090306.297886-14-tudor.ambarus@xxxxxxxxxxxxx
Signed-off-by: Vinod Koul <vkoul@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/dma/at_hdmac.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -256,6 +256,8 @@ static void atc_dostart(struct at_dma_ch
ATC_SPIP_BOUNDARY(first->boundary));
channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) |
ATC_DPIP_BOUNDARY(first->boundary));
+ /* Don't allow CPU to reorder channel enable. */
+ wmb();
dma_writel(atdma, CHER, atchan->mask);
vdbg_dump_regs(atchan);
Patches currently in stable-queue which might be from tudor.ambarus@xxxxxxxxxxxxx are
queue-6.0/dmaengine-at_hdmac-fix-concurrency-problems-by-removing-atc_complete_all.patch
queue-6.0/dmaengine-at_hdmac-start-transfer-for-cyclic-channels-in-issue_pending.patch
queue-6.0/dmaengine-at_hdmac-don-t-start-transactions-at-tx_submit-level.patch
queue-6.0/dmaengine-at_hdmac-fix-at_lli-struct-definition.patch
queue-6.0/dmaengine-at_hdmac-fix-descriptor-handling-when-issuing-it-to-hardware.patch
queue-6.0/dmaengine-at_hdmac-free-the-memset-buf-without-holding-the-chan-lock.patch
queue-6.0/dmaengine-at_hdmac-fix-concurrency-over-the-active-list.patch
queue-6.0/dmaengine-at_hdmac-fix-premature-completion-of-desc-in-issue_pending.patch
queue-6.0/dmaengine-at_hdmac-fix-impossible-condition.patch
queue-6.0/dmaengine-at_hdmac-check-return-code-of-dma_async_device_register.patch
queue-6.0/dmaengine-at_hdmac-don-t-allow-cpu-to-reorder-channel-enable.patch
queue-6.0/dmaengine-at_hdmac-fix-concurrency-over-descriptor.patch
queue-6.0/dmaengine-at_hdmac-protect-atchan-status-with-the-channel-lock.patch
queue-6.0/dmaengine-at_hdmac-fix-completion-of-unissued-descriptor-in-case-of-errors.patch
queue-6.0/dmaengine-at_hdmac-do-not-call-the-complete-callback-on-device_terminate_all.patch
