Patch "drm/amd/display: Set memclk levels to be at least 1 for dcn32" has been added to the 6.0-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/amd/display: Set memclk levels to be at least 1 for dcn32

to the 6.0-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-set-memclk-levels-to-be-at-least-1-f.patch
and it can be found in the queue-6.0 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 4192cd9a4e3bf4b8c067d7820c5ed6112b780577
Author: Dillon Varone <Dillon.Varone@xxxxxxx>
Date:   Thu Oct 20 11:46:48 2022 -0400

    drm/amd/display: Set memclk levels to be at least 1 for dcn32
    
    [ Upstream commit 6cb5cec16c380be4cf9776a8c23b72e9fe742fd1 ]
    
    [Why]
    Cannot report 0 memclk levels even when SMU does not provide any.
    
    [How]
    When memclk levels reported by SMU is 0, set levels to 1.
    
    Tested-by: Mark Broadworth <mark.broadworth@xxxxxxx>
    Reviewed-by: Martin Leung <Martin.Leung@xxxxxxx>
    Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@xxxxxxx>
    Signed-off-by: Dillon Varone <Dillon.Varone@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Cc: stable@xxxxxxxxxxxxxxx # 6.0.x
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index f3090ead9af5..e7f1d5f8166f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -667,6 +667,9 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
 			&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
 			&num_entries_per_clk->num_memclk_levels);
 
+	/* memclk must have at least one level */
+	num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
+
 	dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
 			&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
 			&num_entries_per_clk->num_fclk_levels);



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