This is a note to let you know that I've just added the patch titled
x86/cpufeatures: Move RETPOLINE flags to word 11
to the 4.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
x86-cpufeatures-move-retpoline-flags-to-word-11.patch
and it can be found in the queue-4.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From foo@baz Mon Oct 31 07:55:50 AM CET 2022
From: Suraj Jitindar Singh <surajjs@xxxxxxxxxx>
Date: Thu, 27 Oct 2022 13:54:42 -0700
Subject: x86/cpufeatures: Move RETPOLINE flags to word 11
To: <stable@xxxxxxxxxxxxxxx>
Cc: <surajjs@xxxxxxxxxx>, <sjitindarsingh@xxxxxxxxx>, <cascardo@xxxxxxxxxxxxx>, <kvm@xxxxxxxxxxxxxxx>, <pbonzini@xxxxxxxxxx>, <jpoimboe@xxxxxxxxxx>, <peterz@xxxxxxxxxxxxx>, <x86@xxxxxxxxxx>
Message-ID: <20221027205442.17210-4-surajjs@xxxxxxxxxx>
From: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
commit a883d624aed463c84c22596006e5a96f5b44db31 upstream.
In order to extend the RETPOLINE features to 4, move them to word 11
where there is still room. This mostly keeps DISABLE_RETPOLINE
simple.
Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
Signed-off-by: Borislav Petkov <bp@xxxxxxx>
Reviewed-by: Josh Poimboeuf <jpoimboe@xxxxxxxxxx>
Signed-off-by: Borislav Petkov <bp@xxxxxxx>
Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@xxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/x86/include/asm/cpufeatures.h | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -202,8 +202,8 @@
#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
-#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
-#define X86_FEATURE_RETPOLINE_LFENCE ( 7*32+13) /* "" Use LFENCE for Spectre variant 2 */
+/* FREE! ( 7*32+12) */
+/* FREE! ( 7*32+13) */
#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
#define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */
#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
@@ -283,6 +283,14 @@
#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
#define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
#define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
+/* FREE! (11*32+ 6) */
+/* FREE! (11*32+ 7) */
+/* FREE! (11*32+ 8) */
+/* FREE! (11*32+ 9) */
+/* FREE! (11*32+10) */
+/* FREE! (11*32+11) */
+#define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
+#define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
Patches currently in stable-queue which might be from surajjs@xxxxxxxxxx are
queue-4.14/x86-speculation-disable-rrsba-behavior.patch
queue-4.14/x86-bugs-report-intel-retbleed-vulnerability.patch
queue-4.14/x86-entry-add-kernel-ibrs-implementation.patch
queue-4.14/x86-bugs-warn-when-ibrs-mitigation-is-selected-on-enhanced-ibrs-parts.patch
queue-4.14/x86-cpu-add-a-steppings-field-to-struct-x86_cpu_id.patch
queue-4.14/x86-speculation-fix-spec_ctrl-write-on-smt-state-change.patch
queue-4.14/entel_idle-disable-ibrs-during-long-idle.patch
queue-4.14/x86-speculation-use-cached-host-spec_ctrl-value-for-guest-entry-exit.patch
queue-4.14/x86-speculation-change-fill_return_buffer-to-work-with-objtool.patch
queue-4.14/x86-speculation-add-lfence-to-rsb-fill-sequence.patch
queue-4.14/x86-bugs-report-amd-retbleed-vulnerability.patch
queue-4.14/x86-speculation-add-spectre_v2-ibrs-option-to-support-kernel-ibrs.patch
queue-4.14/x86-bugs-keep-a-per-cpu-ia32_spec_ctrl-value.patch
queue-4.14/x86-speculation-fill-rsb-on-vmexit-for-ibrs.patch
queue-4.14/x86-speculation-fix-rsb-filling-with-config_retpoline-n.patch
queue-4.14/x86-speculation-add-rsb-vm-exit-protections.patch
queue-4.14/x86-bugs-optimize-spec_ctrl-msr-writes.patch
queue-4.14/kvm-vmx-fix-ibrs-handling-after-vmexit.patch
queue-4.14/kvm-vmx-prevent-guest-rsb-poisoning-attacks-with-eibrs.patch
queue-4.14/x86-speculation-fix-firmware-entry-spec_ctrl-handling.patch
queue-4.14/x86-bugs-add-amd-retbleed-boot-parameter.patch
queue-4.14/x86-cpu-add-consistent-cpu-match-macros.patch
queue-4.14/x86-speculation-remove-x86_spec_ctrl_mask.patch
queue-4.14/x86-speculation-use-declare_per_cpu-for-x86_spec_ctrl_current.patch
queue-4.14/x86-cpufeature-fix-various-quality-problems-in-the-asm-cpu_device_hd.h-header.patch
queue-4.14/x86-entry-remove-skip_r11rcx.patch
queue-4.14/revert-x86-cpu-add-a-steppings-field-to-struct-x86_cpu_id.patch
queue-4.14/x86-common-stamp-out-the-stepping-madness.patch
queue-4.14/x86-cpu-amd-enumerate-btc_no.patch
queue-4.14/x86-bugs-add-cannon-lake-to-retbleed-affected-cpu-list.patch
queue-4.14/x86-devicetable-move-x86-specific-macro-out-of-generic-code.patch
queue-4.14/x86-bugs-split-spectre_v2_select_mitigation-and-spectre_v2_user_select_mitigation.patch
queue-4.14/x86-cpufeatures-move-retpoline-flags-to-word-11.patch
queue-4.14/x86-cpufeature-add-facility-to-check-for-min-microcode-revisions.patch
