This is a note to let you know that I've just added the patch titled x86/bugs: Keep a per-CPU IA32_SPEC_CTRL value to the 4.14-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: x86-bugs-keep-a-per-cpu-ia32_spec_ctrl-value.patch and it can be found in the queue-4.14 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From foo@baz Mon Oct 31 07:55:50 AM CET 2022 From: Suraj Jitindar Singh <surajjs@xxxxxxxxxx> Date: Thu, 27 Oct 2022 13:54:51 -0700 Subject: x86/bugs: Keep a per-CPU IA32_SPEC_CTRL value To: <stable@xxxxxxxxxxxxxxx> Cc: <surajjs@xxxxxxxxxx>, <sjitindarsingh@xxxxxxxxx>, <cascardo@xxxxxxxxxxxxx>, <kvm@xxxxxxxxxxxxxxx>, <pbonzini@xxxxxxxxxx>, <jpoimboe@xxxxxxxxxx>, <peterz@xxxxxxxxxxxxx>, <x86@xxxxxxxxxx> Message-ID: <20221027205452.17271-3-surajjs@xxxxxxxxxx> From: Peter Zijlstra <peterz@xxxxxxxxxxxxx> commit caa0ff24d5d0e02abce5e65c3d2b7f20a6617be5 upstream. Due to TIF_SSBD and TIF_SPEC_IB the actual IA32_SPEC_CTRL value can differ from x86_spec_ctrl_base. As such, keep a per-CPU value reflecting the current task's MSR content. [jpoimboe: rename] Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx> Signed-off-by: Borislav Petkov <bp@xxxxxxx> Reviewed-by: Josh Poimboeuf <jpoimboe@xxxxxxxxxx> Signed-off-by: Borislav Petkov <bp@xxxxxxx> Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@xxxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/x86/include/asm/nospec-branch.h | 1 + arch/x86/kernel/cpu/bugs.c | 28 +++++++++++++++++++++++----- arch/x86/kernel/process.c | 2 +- 3 files changed, 25 insertions(+), 6 deletions(-) --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -291,6 +291,7 @@ static inline void indirect_branch_predi /* The Intel SPEC CTRL MSR base value cache */ extern u64 x86_spec_ctrl_base; +extern void write_spec_ctrl_current(u64 val); /* * With retpoline, we must use IBRS to restrict branch prediction --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -47,12 +47,30 @@ static void __init taa_select_mitigation static void __init mmio_select_mitigation(void); static void __init srbds_select_mitigation(void); -/* The base value of the SPEC_CTRL MSR that always has to be preserved. */ +/* The base value of the SPEC_CTRL MSR without task-specific bits set */ u64 x86_spec_ctrl_base; EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); + +/* The current value of the SPEC_CTRL MSR with task-specific bits set */ +DEFINE_PER_CPU(u64, x86_spec_ctrl_current); +EXPORT_SYMBOL_GPL(x86_spec_ctrl_current); + static DEFINE_MUTEX(spec_ctrl_mutex); /* + * Keep track of the SPEC_CTRL MSR value for the current task, which may differ + * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update(). + */ +void write_spec_ctrl_current(u64 val) +{ + if (this_cpu_read(x86_spec_ctrl_current) == val) + return; + + this_cpu_write(x86_spec_ctrl_current, val); + wrmsrl(MSR_IA32_SPEC_CTRL, val); +} + +/* * The vendor and possibly platform specific bits which can be modified in * x86_spec_ctrl_base. */ @@ -1173,7 +1191,7 @@ static void __init spectre_v2_select_mit if (spectre_v2_in_eibrs_mode(mode)) { /* Force it so VMEXIT will restore correctly */ x86_spec_ctrl_base |= SPEC_CTRL_IBRS; - wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); + write_spec_ctrl_current(x86_spec_ctrl_base); } switch (mode) { @@ -1228,7 +1246,7 @@ static void __init spectre_v2_select_mit static void update_stibp_msr(void * __unused) { - wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); + write_spec_ctrl_current(x86_spec_ctrl_base); } /* Update x86_spec_ctrl_base in case SMT state changed. */ @@ -1471,7 +1489,7 @@ static enum ssb_mitigation __init __ssb_ x86_amd_ssb_disable(); } else { x86_spec_ctrl_base |= SPEC_CTRL_SSBD; - wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); + write_spec_ctrl_current(x86_spec_ctrl_base); } } @@ -1676,7 +1694,7 @@ int arch_prctl_spec_ctrl_get(struct task void x86_spec_ctrl_setup_ap(void) { if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) - wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); + write_spec_ctrl_current(x86_spec_ctrl_base); if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) x86_amd_ssb_disable(); --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -435,7 +435,7 @@ static __always_inline void __speculatio } if (updmsr) - wrmsrl(MSR_IA32_SPEC_CTRL, msr); + write_spec_ctrl_current(msr); } static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) Patches currently in stable-queue which might be from surajjs@xxxxxxxxxx are queue-4.14/x86-speculation-disable-rrsba-behavior.patch queue-4.14/x86-bugs-report-intel-retbleed-vulnerability.patch queue-4.14/x86-entry-add-kernel-ibrs-implementation.patch queue-4.14/x86-bugs-warn-when-ibrs-mitigation-is-selected-on-enhanced-ibrs-parts.patch queue-4.14/x86-cpu-add-a-steppings-field-to-struct-x86_cpu_id.patch queue-4.14/x86-speculation-fix-spec_ctrl-write-on-smt-state-change.patch queue-4.14/entel_idle-disable-ibrs-during-long-idle.patch queue-4.14/x86-speculation-use-cached-host-spec_ctrl-value-for-guest-entry-exit.patch queue-4.14/x86-speculation-change-fill_return_buffer-to-work-with-objtool.patch queue-4.14/x86-speculation-add-lfence-to-rsb-fill-sequence.patch queue-4.14/x86-bugs-report-amd-retbleed-vulnerability.patch queue-4.14/x86-speculation-add-spectre_v2-ibrs-option-to-support-kernel-ibrs.patch queue-4.14/x86-bugs-keep-a-per-cpu-ia32_spec_ctrl-value.patch queue-4.14/x86-speculation-fill-rsb-on-vmexit-for-ibrs.patch queue-4.14/x86-speculation-fix-rsb-filling-with-config_retpoline-n.patch queue-4.14/x86-speculation-add-rsb-vm-exit-protections.patch queue-4.14/x86-bugs-optimize-spec_ctrl-msr-writes.patch queue-4.14/kvm-vmx-fix-ibrs-handling-after-vmexit.patch queue-4.14/kvm-vmx-prevent-guest-rsb-poisoning-attacks-with-eibrs.patch queue-4.14/x86-speculation-fix-firmware-entry-spec_ctrl-handling.patch queue-4.14/x86-bugs-add-amd-retbleed-boot-parameter.patch queue-4.14/x86-cpu-add-consistent-cpu-match-macros.patch queue-4.14/x86-speculation-remove-x86_spec_ctrl_mask.patch queue-4.14/x86-speculation-use-declare_per_cpu-for-x86_spec_ctrl_current.patch queue-4.14/x86-cpufeature-fix-various-quality-problems-in-the-asm-cpu_device_hd.h-header.patch queue-4.14/x86-entry-remove-skip_r11rcx.patch queue-4.14/revert-x86-cpu-add-a-steppings-field-to-struct-x86_cpu_id.patch queue-4.14/x86-common-stamp-out-the-stepping-madness.patch queue-4.14/x86-cpu-amd-enumerate-btc_no.patch queue-4.14/x86-bugs-add-cannon-lake-to-retbleed-affected-cpu-list.patch queue-4.14/x86-devicetable-move-x86-specific-macro-out-of-generic-code.patch queue-4.14/x86-bugs-split-spectre_v2_select_mitigation-and-spectre_v2_user_select_mitigation.patch queue-4.14/x86-cpufeatures-move-retpoline-flags-to-word-11.patch queue-4.14/x86-cpufeature-add-facility-to-check-for-min-microcode-revisions.patch