Patch "net: phy: dp83867: Extend RX strap quirk for SGMII mode" has been added to the 5.10-stable tree

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This is a note to let you know that I've just added the patch titled

    net: phy: dp83867: Extend RX strap quirk for SGMII mode

to the 5.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     net-phy-dp83867-extend-rx-strap-quirk-for-sgmii-mode.patch
and it can be found in the queue-5.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 64e9beb9998ad18102560f4328d09e147f1aa484
Author: Harini Katakam <harini.katakam@xxxxxxx>
Date:   Fri Oct 14 12:17:35 2022 +0530

    net: phy: dp83867: Extend RX strap quirk for SGMII mode
    
    [ Upstream commit 0c9efbd5c50c64ead434960a404c9c9a097b0403 ]
    
    When RX strap in HW is not set to MODE 3 or 4, bit 7 and 8 in CF4
    register should be set. The former is already handled in
    dp83867_config_init; add the latter in SGMII specific initialization.
    
    Fixes: 2a10154abcb7 ("net: phy: dp83867: Add TI dp83867 phy")
    Signed-off-by: Harini Katakam <harini.katakam@xxxxxxx>
    Reviewed-by: Andrew Lunn <andrew@xxxxxxx>
    Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index f86acad0aad4..c8031e297faf 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -757,6 +757,14 @@ static int dp83867_config_init(struct phy_device *phydev)
 		else
 			val &= ~DP83867_SGMII_TYPE;
 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
+
+		/* This is a SW workaround for link instability if RX_CTRL is
+		 * not strapped to mode 3 or 4 in HW. This is required for SGMII
+		 * in addition to clearing bit 7, handled above.
+		 */
+		if (dp83867->rxctrl_strap_quirk)
+			phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
+					 BIT(8));
 	}
 
 	val = phy_read(phydev, DP83867_CFG3);



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