Patch "clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent" has been added to the 5.15-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-mediatek-mt8183-mfgcfg-propagate-rate-changes-to.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 38b1a381eee20d9adcf3600b2e162a18800474d0
Author: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
Date:   Tue Sep 27 12:11:20 2022 +0200

    clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent
    
    [ Upstream commit 9f94f545f258b15bfa6357eb62e1e307b712851e ]
    
    The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its
    rate change requests to its parent, so that DVFS for the GPU can work
    properly.
    
    Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support")
    Signed-off-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
    Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
    Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20220927101128.44758-3-angelogioacchino.delregno@xxxxxxxxxxxxx
    Signed-off-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
index 37b4162c5882..3a33014eee7f 100644
--- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
+++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
@@ -18,9 +18,9 @@ static const struct mtk_gate_regs mfg_cg_regs = {
 	.sta_ofs = 0x0,
 };
 
-#define GATE_MFG(_id, _name, _parent, _shift)			\
-	GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift,	\
-		&mtk_clk_gate_ops_setclr)
+#define GATE_MFG(_id, _name, _parent, _shift)				\
+	GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift,	\
+		       &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
 
 static const struct mtk_gate mfg_clks[] = {
 	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)



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