This is a note to let you know that I've just added the patch titled arm64: dts: qcom: sdm845: narrow LLCC address space to the 6.0-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch and it can be found in the queue-6.0 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. commit b2c83d7350882592f9c9be9a163fc5a60704ab00 Author: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Date: Thu Jul 28 13:37:47 2022 +0200 arm64: dts: qcom: sdm845: narrow LLCC address space [ Upstream commit 300b5f661eebefb8571841b78091343eb87eca54 ] The Last Level Cache Controller (LLCC) device does not need to access entire LLCC address space. Currently driver uses only hardware info and status registers which both reside in LLCC0_COMMON range (offset 0x30000, size 0x1000). Narrow the address space to allow binding other drivers to rest of LLCC address space. Cc: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx> Cc: Sibi Sankar <quic_sibis@xxxxxxxxxxx> Reported-by: Steev Klimaszewski <steev@xxxxxxxx> Suggested-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Tested-by: Steev Klimaszewski <steev@xxxxxxxx> Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> Link: https://lore.kernel.org/r/20220728113748.170548-11-krzysztof.kozlowski@xxxxxxxxxx Stable-dep-of: 5a0504945878 ("arm64: dts: qcom: sdm845-xiaomi-polaris: Fix sde_dsi_active pinctrl") Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index f0e286715d1b..4d5ae5897d1d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2138,7 +2138,7 @@ llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; + reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; };