This is a note to let you know that I've just added the patch titled
x86/speculation: Use cached host SPEC_CTRL value for guest entry/exit
to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
x86-speculation-use-cached-host-spec_ctrl-value-for-guest-entry-exit.patch
and it can be found in the queue-5.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From foo@baz Wed Oct 5 12:28:43 PM CEST 2022
From: Thadeu Lima de Souza Cascardo <cascardo@xxxxxxxxxxxxx>
Date: Mon, 3 Oct 2022 10:10:23 -0300
Subject: x86/speculation: Use cached host SPEC_CTRL value for guest entry/exit
To: stable@xxxxxxxxxxxxxxx
Cc: x86@xxxxxxxxxx, kvm@xxxxxxxxxxxxxxx, bp@xxxxxxxxx, pbonzini@xxxxxxxxxx, peterz@xxxxxxxxxxxxx, jpoimboe@xxxxxxxxxx
Message-ID: <20221003131038.12645-23-cascardo@xxxxxxxxxxxxx>
From: Josh Poimboeuf <jpoimboe@xxxxxxxxxx>
commit bbb69e8bee1bd882784947095ffb2bfe0f7c9470 upstream.
There's no need to recalculate the host value for every entry/exit.
Just use the cached value in spec_ctrl_current().
Signed-off-by: Josh Poimboeuf <jpoimboe@xxxxxxxxxx>
Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
Signed-off-by: Borislav Petkov <bp@xxxxxxx>
Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@xxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/x86/kernel/cpu/bugs.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -198,7 +198,7 @@ void __init check_bugs(void)
void
x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
{
- u64 msrval, guestval, hostval = x86_spec_ctrl_base;
+ u64 msrval, guestval, hostval = spec_ctrl_current();
struct thread_info *ti = current_thread_info();
/* Is MSR_SPEC_CTRL implemented ? */
@@ -211,15 +211,6 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl,
guestval = hostval & ~x86_spec_ctrl_mask;
guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
- /* SSBD controlled in MSR_SPEC_CTRL */
- if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
- static_cpu_has(X86_FEATURE_AMD_SSBD))
- hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
-
- /* Conditional STIBP enabled? */
- if (static_branch_unlikely(&switch_to_cond_stibp))
- hostval |= stibp_tif_to_spec_ctrl(ti->flags);
-
if (hostval != guestval) {
msrval = setguest ? guestval : hostval;
wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
@@ -1274,7 +1265,6 @@ static void __init spectre_v2_select_mit
pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
if (spectre_v2_in_ibrs_mode(mode)) {
- /* Force it so VMEXIT will restore correctly */
x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
write_spec_ctrl_current(x86_spec_ctrl_base, true);
}
Patches currently in stable-queue which might be from cascardo@xxxxxxxxxxxxx are
queue-5.4/x86-speculation-disable-rrsba-behavior.patch
queue-5.4/kvm-vmx-flatten-__vmx_vcpu_run.patch
queue-5.4/x86-kvm-vmx-make-noinstr-clean.patch
queue-5.4/revert-x86-speculation-add-rsb-vm-exit-protections.patch
queue-5.4/kvm-vmx-fix-ibrs-handling-after-vmexit.patch
queue-5.4/kvm-vmx-prevent-guest-rsb-poisoning-attacks-with-eibrs.patch
queue-5.4/kvm-nvmx-use-__vmx_vcpu_run-in-nested_vmx_check_vmentry_hw.patch
queue-5.4/x86-bugs-keep-a-per-cpu-ia32_spec_ctrl-value.patch
queue-5.4/x86-cpu-amd-enumerate-btc_no.patch
queue-5.4/x86-speculation-fix-firmware-entry-spec_ctrl-handling.patch
queue-5.4/x86-speculation-add-spectre_v2-ibrs-option-to-support-kernel-ibrs.patch
queue-5.4/x86-cpu-add-consistent-cpu-match-macros.patch
queue-5.4/x86-speculation-remove-x86_spec_ctrl_mask.patch
queue-5.4/x86-bugs-add-cannon-lake-to-retbleed-affected-cpu-list.patch
queue-5.4/x86-bugs-warn-when-ibrs-mitigation-is-selected-on-enhanced-ibrs-parts.patch
queue-5.4/x86-speculation-fill-rsb-on-vmexit-for-ibrs.patch
queue-5.4/x86-cpu-add-a-steppings-field-to-struct-x86_cpu_id.patch
queue-5.4/kvm-vmx-convert-launched-argument-to-flags.patch
queue-5.4/x86-common-stamp-out-the-stepping-madness.patch
queue-5.4/x86-bugs-split-spectre_v2_select_mitigation-and-spectre_v2_user_select_mitigation.patch
queue-5.4/x86-bugs-report-intel-retbleed-vulnerability.patch
queue-5.4/x86-speculation-change-fill_return_buffer-to-work-with-objtool.patch
queue-5.4/x86-cpufeatures-move-retpoline-flags-to-word-11.patch
queue-5.4/x86-speculation-fix-spec_ctrl-write-on-smt-state-change.patch
queue-5.4/kvm-vmx-use-test-reg-reg-instead-of-cmp-0-reg-in-vmenter.s.patch
queue-5.4/x86-bugs-optimize-spec_ctrl-msr-writes.patch
queue-5.4/x86-bugs-report-amd-retbleed-vulnerability.patch
queue-5.4/x86-speculation-fix-rsb-filling-with-config_retpoline-n.patch
queue-5.4/intel_idle-disable-ibrs-during-long-idle.patch
queue-5.4/x86-speculation-use-declare_per_cpu-for-x86_spec_ctrl_current.patch
queue-5.4/x86-entry-remove-skip_r11rcx.patch
queue-5.4/x86-speculation-use-cached-host-spec_ctrl-value-for-guest-entry-exit.patch
queue-5.4/x86-devicetable-move-x86-specific-macro-out-of-generic-code.patch
queue-5.4/x86-bugs-add-amd-retbleed-boot-parameter.patch
queue-5.4/x86-entry-add-kernel-ibrs-implementation.patch
queue-5.4/revert-x86-cpu-add-a-steppings-field-to-struct-x86_cpu_id.patch
queue-5.4/x86-speculation-add-rsb-vm-exit-protections.patch
