This is a note to let you know that I've just added the patch titled x86/bugs: Optimize SPEC_CTRL MSR writes to the 5.4-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: x86-bugs-optimize-spec_ctrl-msr-writes.patch and it can be found in the queue-5.4 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From foo@baz Wed Oct 5 12:28:43 PM CEST 2022 From: Thadeu Lima de Souza Cascardo <cascardo@xxxxxxxxxxxxx> Date: Mon, 3 Oct 2022 10:10:14 -0300 Subject: x86/bugs: Optimize SPEC_CTRL MSR writes To: stable@xxxxxxxxxxxxxxx Cc: x86@xxxxxxxxxx, kvm@xxxxxxxxxxxxxxx, bp@xxxxxxxxx, pbonzini@xxxxxxxxxx, peterz@xxxxxxxxxxxxx, jpoimboe@xxxxxxxxxx Message-ID: <20221003131038.12645-14-cascardo@xxxxxxxxxxxxx> From: Peter Zijlstra <peterz@xxxxxxxxxxxxx> commit c779bc1a9002fa474175b80e72b85c9bf628abb0 upstream. When changing SPEC_CTRL for user control, the WRMSR can be delayed until return-to-user when KERNEL_IBRS has been enabled. This avoids an MSR write during context switch. Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx> Signed-off-by: Borislav Petkov <bp@xxxxxxx> Reviewed-by: Josh Poimboeuf <jpoimboe@xxxxxxxxxx> Signed-off-by: Borislav Petkov <bp@xxxxxxx> Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@xxxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/x86/include/asm/nospec-branch.h | 2 +- arch/x86/kernel/cpu/bugs.c | 18 ++++++++++++------ arch/x86/kernel/process.c | 2 +- 3 files changed, 14 insertions(+), 8 deletions(-) --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -297,7 +297,7 @@ static inline void indirect_branch_predi /* The Intel SPEC CTRL MSR base value cache */ extern u64 x86_spec_ctrl_base; -extern void write_spec_ctrl_current(u64 val); +extern void write_spec_ctrl_current(u64 val, bool force); /* * With retpoline, we must use IBRS to restrict branch prediction --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -61,13 +61,19 @@ static DEFINE_MUTEX(spec_ctrl_mutex); * Keep track of the SPEC_CTRL MSR value for the current task, which may differ * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update(). */ -void write_spec_ctrl_current(u64 val) +void write_spec_ctrl_current(u64 val, bool force) { if (this_cpu_read(x86_spec_ctrl_current) == val) return; this_cpu_write(x86_spec_ctrl_current, val); - wrmsrl(MSR_IA32_SPEC_CTRL, val); + + /* + * When KERNEL_IBRS this MSR is written on return-to-user, unless + * forced the update can be delayed until that time. + */ + if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) + wrmsrl(MSR_IA32_SPEC_CTRL, val); } /* @@ -1195,7 +1201,7 @@ static void __init spectre_v2_select_mit if (spectre_v2_in_eibrs_mode(mode)) { /* Force it so VMEXIT will restore correctly */ x86_spec_ctrl_base |= SPEC_CTRL_IBRS; - write_spec_ctrl_current(x86_spec_ctrl_base); + write_spec_ctrl_current(x86_spec_ctrl_base, true); } switch (mode) { @@ -1250,7 +1256,7 @@ static void __init spectre_v2_select_mit static void update_stibp_msr(void * __unused) { - write_spec_ctrl_current(x86_spec_ctrl_base); + write_spec_ctrl_current(x86_spec_ctrl_base, true); } /* Update x86_spec_ctrl_base in case SMT state changed. */ @@ -1493,7 +1499,7 @@ static enum ssb_mitigation __init __ssb_ x86_amd_ssb_disable(); } else { x86_spec_ctrl_base |= SPEC_CTRL_SSBD; - write_spec_ctrl_current(x86_spec_ctrl_base); + write_spec_ctrl_current(x86_spec_ctrl_base, true); } } @@ -1710,7 +1716,7 @@ int arch_prctl_spec_ctrl_get(struct task void x86_spec_ctrl_setup_ap(void) { if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) - write_spec_ctrl_current(x86_spec_ctrl_base); + write_spec_ctrl_current(x86_spec_ctrl_base, true); if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) x86_amd_ssb_disable(); --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -449,7 +449,7 @@ static __always_inline void __speculatio } if (updmsr) - write_spec_ctrl_current(msr); + write_spec_ctrl_current(msr, false); } static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) Patches currently in stable-queue which might be from cascardo@xxxxxxxxxxxxx are queue-5.4/x86-speculation-disable-rrsba-behavior.patch queue-5.4/kvm-vmx-flatten-__vmx_vcpu_run.patch queue-5.4/x86-kvm-vmx-make-noinstr-clean.patch queue-5.4/revert-x86-speculation-add-rsb-vm-exit-protections.patch queue-5.4/kvm-vmx-fix-ibrs-handling-after-vmexit.patch queue-5.4/kvm-vmx-prevent-guest-rsb-poisoning-attacks-with-eibrs.patch queue-5.4/kvm-nvmx-use-__vmx_vcpu_run-in-nested_vmx_check_vmentry_hw.patch queue-5.4/x86-bugs-keep-a-per-cpu-ia32_spec_ctrl-value.patch queue-5.4/x86-cpu-amd-enumerate-btc_no.patch queue-5.4/x86-speculation-fix-firmware-entry-spec_ctrl-handling.patch queue-5.4/x86-speculation-add-spectre_v2-ibrs-option-to-support-kernel-ibrs.patch queue-5.4/x86-cpu-add-consistent-cpu-match-macros.patch queue-5.4/x86-speculation-remove-x86_spec_ctrl_mask.patch queue-5.4/x86-bugs-add-cannon-lake-to-retbleed-affected-cpu-list.patch queue-5.4/x86-bugs-warn-when-ibrs-mitigation-is-selected-on-enhanced-ibrs-parts.patch queue-5.4/x86-speculation-fill-rsb-on-vmexit-for-ibrs.patch queue-5.4/x86-cpu-add-a-steppings-field-to-struct-x86_cpu_id.patch queue-5.4/kvm-vmx-convert-launched-argument-to-flags.patch queue-5.4/x86-common-stamp-out-the-stepping-madness.patch queue-5.4/x86-bugs-split-spectre_v2_select_mitigation-and-spectre_v2_user_select_mitigation.patch queue-5.4/x86-bugs-report-intel-retbleed-vulnerability.patch queue-5.4/x86-speculation-change-fill_return_buffer-to-work-with-objtool.patch queue-5.4/x86-cpufeatures-move-retpoline-flags-to-word-11.patch queue-5.4/x86-speculation-fix-spec_ctrl-write-on-smt-state-change.patch queue-5.4/kvm-vmx-use-test-reg-reg-instead-of-cmp-0-reg-in-vmenter.s.patch queue-5.4/x86-bugs-optimize-spec_ctrl-msr-writes.patch queue-5.4/x86-bugs-report-amd-retbleed-vulnerability.patch queue-5.4/x86-speculation-fix-rsb-filling-with-config_retpoline-n.patch queue-5.4/intel_idle-disable-ibrs-during-long-idle.patch queue-5.4/x86-speculation-use-declare_per_cpu-for-x86_spec_ctrl_current.patch queue-5.4/x86-entry-remove-skip_r11rcx.patch queue-5.4/x86-speculation-use-cached-host-spec_ctrl-value-for-guest-entry-exit.patch queue-5.4/x86-devicetable-move-x86-specific-macro-out-of-generic-code.patch queue-5.4/x86-bugs-add-amd-retbleed-boot-parameter.patch queue-5.4/x86-entry-add-kernel-ibrs-implementation.patch queue-5.4/revert-x86-cpu-add-a-steppings-field-to-struct-x86_cpu_id.patch queue-5.4/x86-speculation-add-rsb-vm-exit-protections.patch