Patch "drm/msm/dsi: fix the inconsistent indenting" has been added to the 4.19-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/msm/dsi: fix the inconsistent indenting

to the 4.19-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-msm-dsi-fix-the-inconsistent-indenting.patch
and it can be found in the queue-4.19 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 0d1a1119afc4ab18a3cfdef6d37b5bec0a54ad99
Author: sunliming <sunliming@xxxxxxxxxx>
Date:   Tue Jul 19 09:56:22 2022 +0800

    drm/msm/dsi: fix the inconsistent indenting
    
    [ Upstream commit 2f25a1fb4ec516c5ad67afd754334b491b9f09a5 ]
    
    Fix the inconsistent indenting in function msm_dsi_dphy_timing_calc_v3().
    
    Fix the following smatch warnings:
    
    drivers/gpu/drm/msm/dsi/phy/dsi_phy.c:350 msm_dsi_dphy_timing_calc_v3() warn: inconsistent indenting
    
    Fixes: f1fa7ff44056 ("drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY")
    Reported-by: kernel test robot <lkp@xxxxxxxxx>
    Signed-off-by: sunliming <sunliming@xxxxxxxxxx>
    Reviewed-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
    Patchwork: https://patchwork.freedesktop.org/patch/494662/
    Link: https://lore.kernel.org/r/20220719015622.646718-1-sunliming@xxxxxxxxxx
    Signed-off-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index f01e245cd0eee..bed0cd72e3ebd 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -355,7 +355,7 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
 	} else {
 		timing->shared_timings.clk_pre =
 			linear_inter(tmax, tmin, pcnt2, 0, false);
-			timing->shared_timings.clk_pre_inc_by_2 = 0;
+		timing->shared_timings.clk_pre_inc_by_2 = 0;
 	}
 
 	timing->ta_go = 3;



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