Patch "KVM: set_msr_mce: Permit guests to ignore single-bit ECC errors" has been added to the 5.10-stable tree

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This is a note to let you know that I've just added the patch titled

    KVM: set_msr_mce: Permit guests to ignore single-bit ECC errors

to the 5.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     kvm-set_msr_mce-permit-guests-to-ignore-single-bit-e.patch
and it can be found in the queue-5.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 3ab0d29fb5f6584612a84c441dcbc2eb184836b7
Author: Lev Kujawski <lkujaw@xxxxxxxxxxxxxx>
Date:   Sat May 21 08:15:11 2022 +0000

    KVM: set_msr_mce: Permit guests to ignore single-bit ECC errors
    
    [ Upstream commit 0471a7bd1bca2a47a5f378f2222c5cf39ce94152 ]
    
    Certain guest operating systems (e.g., UNIXWARE) clear bit 0 of
    MC1_CTL to ignore single-bit ECC data errors.  Single-bit ECC data
    errors are always correctable and thus are safe to ignore because they
    are informational in nature rather than signaling a loss of data
    integrity.
    
    Prior to this patch, these guests would crash upon writing MC1_CTL,
    with resultant error messages like the following:
    
    error: kvm run failed Operation not permitted
    EAX=fffffffe EBX=fffffffe ECX=00000404 EDX=ffffffff
    ESI=ffffffff EDI=00000001 EBP=fffdaba4 ESP=fffdab20
    EIP=c01333a5 EFL=00000246 [---Z-P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
    ES =0108 00000000 ffffffff 00c09300 DPL=0 DS   [-WA]
    CS =0100 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
    SS =0108 00000000 ffffffff 00c09300 DPL=0 DS   [-WA]
    DS =0108 00000000 ffffffff 00c09300 DPL=0 DS   [-WA]
    FS =0000 00000000 ffffffff 00c00000
    GS =0000 00000000 ffffffff 00c00000
    LDT=0118 c1026390 00000047 00008200 DPL=0 LDT
    TR =0110 ffff5af0 00000067 00008b00 DPL=0 TSS32-busy
    GDT=     ffff5020 000002cf
    IDT=     ffff52f0 000007ff
    CR0=8001003b CR2=00000000 CR3=0100a000 CR4=00000230
    DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
    DR6=ffff0ff0 DR7=00000400
    EFER=0000000000000000
    Code=08 89 01 89 51 04 c3 8b 4c 24 08 8b 01 8b 51 04 8b 4c 24 04 <0f>
    30 c3 f7 05 a4 6d ff ff 10 00 00 00 74 03 0f 31 c3 33 c0 33 d2 c3 8d
    74 26 00 0f 31 c3
    
    Signed-off-by: Lev Kujawski <lkujaw@xxxxxxxxxxxxxx>
    Message-Id: <20220521081511.187388-1-lkujaw@xxxxxxxxxxxxxx>
    Signed-off-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 29a8ca95c581..23a5e5880615 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -2862,10 +2862,13 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			/* only 0 or all 1s can be written to IA32_MCi_CTL
 			 * some Linux kernels though clear bit 10 in bank 4 to
 			 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
-			 * this to avoid an uncatched #GP in the guest
+			 * this to avoid an uncatched #GP in the guest.
+			 *
+			 * UNIXWARE clears bit 0 of MC1_CTL to ignore
+			 * correctable, single-bit ECC data errors.
 			 */
 			if ((offset & 0x3) == 0 &&
-			    data != 0 && (data | (1 << 10)) != ~(u64)0)
+			    data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
 				return -1;
 
 			/* MCi_STATUS */



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