Patch "mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R" has been added to the 5.4-stable tree

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This is a note to let you know that I've just added the patch titled

    mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R

to the 5.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     mmc-sdhci-of-at91-fix-set_uhs_signaling-rewriting-of.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 555577fc605d347b0308c5eab2dfc61c9a5cb59f
Author: Eugen Hristev <eugen.hristev@xxxxxxxxxxxxx>
Date:   Thu Jun 30 12:09:26 2022 +0300

    mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R
    
    [ Upstream commit 5987e6ded29d52e42fc7b06aa575c60a25eee38e ]
    
    In set_uhs_signaling, the DDR bit is being set by fully writing the MC1R
    register.
    This can lead to accidental erase of certain bits in this register.
    Avoid this by doing a read-modify-write operation.
    
    Fixes: d0918764c17b ("mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection")
    Signed-off-by: Eugen Hristev <eugen.hristev@xxxxxxxxxxxxx>
    Tested-by: Karl Olsen <karl@xxxxxxxxxxxxxxxxx>
    Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
    Link: https://lore.kernel.org/r/20220630090926.15061-1-eugen.hristev@xxxxxxxxxxxxx
    Signed-off-by: Ulf Hansson <ulf.hansson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
index 881f8138e7de..03698d78a402 100644
--- a/drivers/mmc/host/sdhci-of-at91.c
+++ b/drivers/mmc/host/sdhci-of-at91.c
@@ -109,8 +109,13 @@ static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
 					 unsigned int timing)
 {
-	if (timing == MMC_TIMING_MMC_DDR52)
-		sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
+	u8 mc1r;
+
+	if (timing == MMC_TIMING_MMC_DDR52) {
+		mc1r = sdhci_readb(host, SDMMC_MC1R);
+		mc1r |= SDMMC_MC1R_DDR;
+		sdhci_writeb(host, mc1r, SDMMC_MC1R);
+	}
 	sdhci_set_uhs_signaling(host, timing);
 }
 



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