Patch "drm/vc4: hdmi: Correct HDMI timing registers for interlaced modes" has been added to the 5.19-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/vc4: hdmi: Correct HDMI timing registers for interlaced modes

to the 5.19-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-vc4-hdmi-correct-hdmi-timing-registers-for-inter.patch
and it can be found in the queue-5.19 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 33c31d5b87ed4a1d5ac96dc5de2ac135a13566db
Author: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>
Date:   Mon Jun 13 16:47:59 2022 +0200

    drm/vc4: hdmi: Correct HDMI timing registers for interlaced modes
    
    [ Upstream commit fb10dc451c0f15e3c19798a2f41d357f3f7576f5 ]
    
    For interlaced modes the timings were not being correctly
    programmed into the HDMI block, so correct them.
    
    Fixes: 8323989140f3 ("drm/vc4: hdmi: Support the BCM2711 HDMI controllers")
    Signed-off-by: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20220613144800.326124-33-maxime@xxxxxxxxxx
    Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 3829e13c8627..ad7fcfa5a068 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1040,13 +1040,13 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 		     VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 				   VC5_HDMI_VERTA_VFP) |
 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
-	u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
-		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
-				   interlaced,
+	u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
+				   VC5_HDMI_VERTB_VSPO) |
+		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 				   VC4_HDMI_VERTB_VBP));
 	u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 			  VC4_SET_FIELD(mode->crtc_vtotal -
-					mode->crtc_vsync_end,
+					mode->crtc_vsync_end - interlaced,
 					VC4_HDMI_VERTB_VBP));
 	unsigned long flags;
 	unsigned char gcp;



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