This is a note to let you know that I've just added the patch titled riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit to the 5.18-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: riscv-lib-uaccess-fix-csr_status-sr_sum-bit.patch and it can be found in the queue-5.18 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From c08b4848f596fd95543197463b5162bd7bab2442 Mon Sep 17 00:00:00 2001 From: Chen Lifu <chenlifu@xxxxxxxxxx> Date: Wed, 15 Jun 2022 09:47:14 +0800 Subject: riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit From: Chen Lifu <chenlifu@xxxxxxxxxx> commit c08b4848f596fd95543197463b5162bd7bab2442 upstream. Since commit 5d8544e2d007 ("RISC-V: Generic library routines and assembly") and commit ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code"), if __clear_user and __copy_user return from an fixup branch, CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that S-mode memory accesses to pages that are accessible by U-mode will success. Disable S-mode access to U-mode memory should clear SR_SUM bit. Fixes: 5d8544e2d007 ("RISC-V: Generic library routines and assembly") Fixes: ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code") Signed-off-by: Chen Lifu <chenlifu@xxxxxxxxxx> Reviewed-by: Ben Dooks <ben.dooks@xxxxxxxxxxxxxxx> Link: https://lore.kernel.org/r/20220615014714.1650349-1-chenlifu@xxxxxxxxxx Cc: stable@xxxxxxxxxxxxxxx Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/riscv/lib/uaccess.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -175,7 +175,7 @@ ENTRY(__asm_copy_from_user) /* Exception fixup code */ 10: /* Disable access to user memory */ - csrs CSR_STATUS, t6 + csrc CSR_STATUS, t6 mv a0, t5 ret ENDPROC(__asm_copy_to_user) @@ -227,7 +227,7 @@ ENTRY(__clear_user) /* Exception fixup code */ 11: /* Disable access to user memory */ - csrs CSR_STATUS, t6 + csrc CSR_STATUS, t6 mv a0, a1 ret ENDPROC(__clear_user) Patches currently in stable-queue which might be from chenlifu@xxxxxxxxxx are queue-5.18/riscv-lib-uaccess-fix-csr_status-sr_sum-bit.patch