This is a note to let you know that I've just added the patch titled
KVM: SVM: Disable SEV-ES support if MMIO caching is disable
to the 5.19-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
kvm-svm-disable-sev-es-support-if-mmio-caching-is-disable.patch
and it can be found in the queue-5.19 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 0c29397ac1fdd64ae59941a477511a05e61a4754 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@xxxxxxxxxx>
Date: Wed, 3 Aug 2022 22:49:57 +0000
Subject: KVM: SVM: Disable SEV-ES support if MMIO caching is disable
From: Sean Christopherson <seanjc@xxxxxxxxxx>
commit 0c29397ac1fdd64ae59941a477511a05e61a4754 upstream.
Disable SEV-ES if MMIO caching is disabled as SEV-ES relies on MMIO SPTEs
generating #NPF(RSVD), which are reflected by the CPU into the guest as
a #VC. With SEV-ES, the untrusted host, a.k.a. KVM, doesn't have access
to the guest instruction stream or register state and so can't directly
emulate in response to a #NPF on an emulated MMIO GPA. Disabling MMIO
caching means guest accesses to emulated MMIO ranges cause #NPF(!PRESENT),
and those flavors of #NPF cause automatic VM-Exits, not #VC.
Adjust KVM's MMIO masks to account for the C-bit location prior to doing
SEV(-ES) setup, and document that dependency between adjusting the MMIO
SPTE mask and SEV(-ES) setup.
Fixes: b09763da4dd8 ("KVM: x86/mmu: Add module param to disable MMIO caching (for testing)")
Reported-by: Michael Roth <michael.roth@xxxxxxx>
Tested-by: Michael Roth <michael.roth@xxxxxxx>
Cc: Tom Lendacky <thomas.lendacky@xxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
Message-Id: <20220803224957.1285926-4-seanjc@xxxxxxxxxx>
Signed-off-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/x86/kvm/mmu.h | 2 ++
arch/x86/kvm/mmu/spte.c | 1 +
arch/x86/kvm/mmu/spte.h | 2 --
arch/x86/kvm/svm/sev.c | 10 ++++++++++
arch/x86/kvm/svm/svm.c | 9 ++++++---
5 files changed, 19 insertions(+), 5 deletions(-)
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -11,6 +11,8 @@
#define PT32_PT_BITS 10
#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
+extern bool __read_mostly enable_mmio_caching;
+
#define PT_WRITABLE_SHIFT 1
#define PT_USER_SHIFT 2
--- a/arch/x86/kvm/mmu/spte.c
+++ b/arch/x86/kvm/mmu/spte.c
@@ -21,6 +21,7 @@
bool __read_mostly enable_mmio_caching = true;
module_param_named(mmio_caching, enable_mmio_caching, bool, 0444);
+EXPORT_SYMBOL_GPL(enable_mmio_caching);
u64 __read_mostly shadow_host_writable_mask;
u64 __read_mostly shadow_mmu_writable_mask;
--- a/arch/x86/kvm/mmu/spte.h
+++ b/arch/x86/kvm/mmu/spte.h
@@ -5,8 +5,6 @@
#include "mmu_internal.h"
-extern bool __read_mostly enable_mmio_caching;
-
/*
* A MMU present SPTE is backed by actual memory and may or may not be present
* in hardware. E.g. MMIO SPTEs are not considered present. Use bit 11, as it
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -22,6 +22,7 @@
#include <asm/trapnr.h>
#include <asm/fpu/xcr.h>
+#include "mmu.h"
#include "x86.h"
#include "svm.h"
#include "svm_ops.h"
@@ -2221,6 +2222,15 @@ void __init sev_hardware_setup(void)
if (!sev_es_enabled)
goto out;
+ /*
+ * SEV-ES requires MMIO caching as KVM doesn't have access to the guest
+ * instruction stream, i.e. can't emulate in response to a #NPF and
+ * instead relies on #NPF(RSVD) being reflected into the guest as #VC
+ * (the guest can then do a #VMGEXIT to request MMIO emulation).
+ */
+ if (!enable_mmio_caching)
+ goto out;
+
/* Does the CPU support SEV-ES? */
if (!boot_cpu_has(X86_FEATURE_SEV_ES))
goto out;
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -4897,13 +4897,16 @@ static __init int svm_hardware_setup(voi
/* Setup shadow_me_value and shadow_me_mask */
kvm_mmu_set_me_spte_mask(sme_me_mask, sme_me_mask);
- /* Note, SEV setup consumes npt_enabled. */
+ svm_adjust_mmio_mask();
+
+ /*
+ * Note, SEV setup consumes npt_enabled and enable_mmio_caching (which
+ * may be modified by svm_adjust_mmio_mask()).
+ */
sev_hardware_setup();
svm_hv_hardware_setup();
- svm_adjust_mmio_mask();
-
for_each_possible_cpu(cpu) {
r = svm_cpu_init(cpu);
if (r)
Patches currently in stable-queue which might be from seanjc@xxxxxxxxxx are
queue-5.19/kvm-x86-mmu-treat-nx-as-a-valid-spte-bit-for-npt.patch
queue-5.19/kvm-x86-xen-initialize-xen-timer-only-once.patch
queue-5.19/kvm-x86-tag-kvm_mmu_x86_module_init-with-__init.patch
queue-5.19/kvm-x86-xen-stop-xen-timer-before-changing-irq.patch
queue-5.19/kvm-put-the-extra-pfn-reference-when-reusing-a-pfn-in-the-gpc-cache.patch
queue-5.19/kvm-drop-unused-gpa-param-from-gfn-pfn-cache-s-__release_gpc-helper.patch
queue-5.19/kvm-nvmx-let-userspace-set-nvmx-msr-to-any-_host_-supported-value.patch
queue-5.19/kvm-svm-disable-sev-es-support-if-mmio-caching-is-disable.patch
queue-5.19/kvm-x86-mmu-fully-re-evaluate-mmio-caching-when-spte-masks-change.patch
queue-5.19/kvm-x86-set-error-code-to-segment-selector-on-lldt-ltr-non-canonical-gp.patch
queue-5.19/kvm-nvmx-inject-ud-if-vmxon-is-attempted-with-incompatible-cr0-cr4.patch
queue-5.19/kvm-do-not-incorporate-page-offset-into-gfn-pfn-cache-user-address.patch
queue-5.19/kvm-svm-don-t-bug-if-userspace-injects-an-interrupt-with-gif-0.patch
queue-5.19/kvm-nvmx-snapshot-pre-vm-enter-bndcfgs-for-nested_run_pending-case.patch
queue-5.19/kvm-x86-split-kvm_is_valid_cr4-and-export-only-the-non-vendor-bits.patch
queue-5.19/kvm-fix-multiple-races-in-gfn-pfn-cache-refresh.patch
queue-5.19/kvm-fully-serialize-gfn-pfn-cache-refresh-via-mutex.patch
queue-5.19/kvm-x86-mark-tss-busy-during-ltr-emulation-_after_-all-fault-checks.patch
queue-5.19/kvm-nvmx-account-for-kvm-reserved-cr4-bits-in-consistency-checks.patch
queue-5.19/kvm-nvmx-snapshot-pre-vm-enter-debugctl-for-nested_run_pending-case.patch
