This is a note to let you know that I've just added the patch titled x86/speculation: Remove x86_spec_ctrl_mask to the 5.10-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: x86-speculation-remove-x86_spec_ctrl_mask.patch and it can be found in the queue-5.10 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From foo@baz Tue Jul 12 05:07:35 PM CEST 2022 From: Josh Poimboeuf <jpoimboe@xxxxxxxxxx> Date: Fri, 17 Jun 2022 12:12:48 -0700 Subject: x86/speculation: Remove x86_spec_ctrl_mask From: Josh Poimboeuf <jpoimboe@xxxxxxxxxx> commit acac5e98ef8d638a411cfa2ee676c87e1973f126 upstream. This mask has been made redundant by kvm_spec_ctrl_test_value(). And it doesn't even work when MSR interception is disabled, as the guest can just write to SPEC_CTRL directly. Signed-off-by: Josh Poimboeuf <jpoimboe@xxxxxxxxxx> Signed-off-by: Borislav Petkov <bp@xxxxxxx> Reviewed-by: Paolo Bonzini <pbonzini@xxxxxxxxxx> Signed-off-by: Borislav Petkov <bp@xxxxxxx> Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@xxxxxxxxxxxxx> Signed-off-by: Ben Hutchings <ben@xxxxxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/x86/kernel/cpu/bugs.c | 31 +------------------------------ 1 file changed, 1 insertion(+), 30 deletions(-) --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -85,12 +85,6 @@ u64 spec_ctrl_current(void) EXPORT_SYMBOL_GPL(spec_ctrl_current); /* - * The vendor and possibly platform specific bits which can be modified in - * x86_spec_ctrl_base. - */ -static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; - -/* * AMD specific MSR info for Speculative Store Bypass control. * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). */ @@ -138,10 +132,6 @@ void __init check_bugs(void) if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); - /* Allow STIBP in MSR_SPEC_CTRL if supported */ - if (boot_cpu_has(X86_FEATURE_STIBP)) - x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; - /* Select the proper CPU mitigations before patching alternatives: */ spectre_v1_select_mitigation(); spectre_v2_select_mitigation(); @@ -199,19 +189,10 @@ void __init check_bugs(void) void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) { - u64 msrval, guestval, hostval = spec_ctrl_current(); + u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current(); struct thread_info *ti = current_thread_info(); - /* Is MSR_SPEC_CTRL implemented ? */ if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { - /* - * Restrict guest_spec_ctrl to supported values. Clear the - * modifiable bits in the host base value and or the - * modifiable bits from the guest value. - */ - guestval = hostval & ~x86_spec_ctrl_mask; - guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; - if (hostval != guestval) { msrval = setguest ? guestval : hostval; wrmsrl(MSR_IA32_SPEC_CTRL, msrval); @@ -1622,16 +1603,6 @@ static enum ssb_mitigation __init __ssb_ } /* - * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper - * bit in the mask to allow guests to use the mitigation even in the - * case where the host does not enable it. - */ - if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || - static_cpu_has(X86_FEATURE_AMD_SSBD)) { - x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; - } - - /* * We have three CPU feature flags that are in play here: * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass Patches currently in stable-queue which might be from jpoimboe@xxxxxxxxxx are queue-5.10/x86-sev-avoid-using-__x86_return_thunk.patch queue-5.10/x86-ftrace-use-alternative-ret-encoding.patch queue-5.10/objtool-re-add-unwind_hint_-save_restore.patch queue-5.10/x86-bugs-add-retbleed-ibpb.patch queue-5.10/x86-retpoline-cleanup-some-ifdefery.patch queue-5.10/kvm-vmx-flatten-__vmx_vcpu_run.patch queue-5.10/x86-cpu-amd-add-spectral-chicken.patch queue-5.10/kvm-vmx-fix-ibrs-handling-after-vmexit.patch queue-5.10/kvm-vmx-prevent-guest-rsb-poisoning-attacks-with-eibrs.patch queue-5.10/x86-vsyscall_emu-64-don-t-use-ret-in-vsyscall-emulation.patch queue-5.10/objtool-skip-non-text-sections-when-adding-return-thunk-sites.patch queue-5.10/x86-bugs-do-ibpb-fallback-check-only-once.patch queue-5.10/x86-add-magic-amd-return-thunk.patch queue-5.10/x86-bugs-keep-a-per-cpu-ia32_spec_ctrl-value.patch queue-5.10/x86-objtool-create-.return_sites.patch queue-5.10/x86-kvm-fix-setcc-emulation-for-return-thunks.patch queue-5.10/x86-retpoline-swizzle-retpoline-thunk.patch queue-5.10/x86-speculation-fix-firmware-entry-spec_ctrl-handling.patch queue-5.10/objtool-fix-symbol-creation.patch queue-5.10/x86-speculation-add-spectre_v2-ibrs-option-to-support-kernel-ibrs.patch queue-5.10/x86-undo-return-thunk-damage.patch queue-5.10/x86-speculation-remove-x86_spec_ctrl_mask.patch queue-5.10/x86-speculation-fill-rsb-on-vmexit-for-ibrs.patch queue-5.10/objtool-add-entry-unret-validation.patch queue-5.10/kvm-vmx-convert-launched-argument-to-flags.patch queue-5.10/x86-bpf-use-alternative-ret-encoding.patch queue-5.10/x86-bugs-split-spectre_v2_select_mitigation-and-spectre_v2_user_select_mitigation.patch queue-5.10/x86-bugs-report-intel-retbleed-vulnerability.patch queue-5.10/x86-cpufeatures-move-retpoline-flags-to-word-11.patch queue-5.10/x86-speculation-fix-spec_ctrl-write-on-smt-state-change.patch queue-5.10/x86-retpoline-use-mfunction-return.patch queue-5.10/x86-xen-rename-sys-entry-points.patch queue-5.10/x86-bugs-optimize-spec_ctrl-msr-writes.patch queue-5.10/x86-bugs-report-amd-retbleed-vulnerability.patch queue-5.10/x86-static_call-use-alternative-ret-encoding.patch queue-5.10/x86-speculation-fix-rsb-filling-with-config_retpoline-n.patch queue-5.10/x86-use-return-thunk-in-asm-code.patch queue-5.10/intel_idle-disable-ibrs-during-long-idle.patch queue-5.10/x86-speculation-use-cached-host-spec_ctrl-value-for-guest-entry-exit.patch queue-5.10/x86-bugs-add-amd-retbleed-boot-parameter.patch queue-5.10/x86-entry-add-kernel-ibrs-implementation.patch queue-5.10/objtool-treat-.text.__x86.-as-noinstr.patch queue-5.10/objtool-update-retpoline-validation.patch