Patch "serial: sifive: Report actual baud base rather than fixed 115200" has been added to the 5.18-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    serial: sifive: Report actual baud base rather than fixed 115200

to the 5.18-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     serial-sifive-report-actual-baud-base-rather-than-fi.patch
and it can be found in the queue-5.18 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 031ad5eb7904ae07047c61ee7b2f8a7f3d97dc66
Author: Maciej W. Rozycki <macro@xxxxxxxxxxx>
Date:   Fri Apr 29 21:40:18 2022 +0100

    serial: sifive: Report actual baud base rather than fixed 115200
    
    [ Upstream commit 0a7ff843d507ce2cca2c3b7e169ee56e28133530 ]
    
    The base baud value reported is supposed to be the highest baud rate
    that can be set for a serial port.  The SiFive FU740-C000 SOC's on-chip
    UART supports baud rates of up to 1/16 of the input clock rate, which is
    the bus clock `tlclk'[1], often at 130MHz in the case of the HiFive
    Unmatched board.
    
    However the sifive UART driver reports a fixed value of 115200 instead:
    
    10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 1, base_baud = 115200) is a SiFive UART v0
    10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 2, base_baud = 115200) is a SiFive UART v0
    
    even though we already support setting higher baud rates, e.g.:
    
    $ tty
    /dev/ttySIF1
    $ stty speed
    230400
    
    The baud base value is computed by the serial core by dividing the UART
    clock recorded in `struct uart_port' by 16, which is also the minimum
    value of the clock divider supported, so correct the baud base value
    reported by setting the UART clock recorded to the input clock rate
    rather than 115200:
    
    10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 1, base_baud = 8125000) is a SiFive UART v0
    10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 2, base_baud = 8125000) is a SiFive UART v0
    
    References:
    
    [1] "SiFive FU740-C000 Manual", v1p3, SiFive, Inc., August 13, 2021,
        Section 16.9 "Baud Rate Divisor Register (div)", pp.143-144
    
    Signed-off-by: Maciej W. Rozycki <macro@xxxxxxxxxxx>
    Fixes: 1f1496a923b6 ("riscv: Fix sifive serial driver")
    Link: https://lore.kernel.org/r/alpine.DEB.2.21.2204291656280.9383@xxxxxxxxxxxxxxxxx
    Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c
index f5ac14c384c4..6140166b7ed5 100644
--- a/drivers/tty/serial/sifive.c
+++ b/drivers/tty/serial/sifive.c
@@ -998,7 +998,7 @@ static int sifive_serial_probe(struct platform_device *pdev)
 	/* Set up clock divider */
 	ssp->clkin_rate = clk_get_rate(ssp->clk);
 	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
-	ssp->port.uartclk = ssp->baud_rate * 16;
+	ssp->port.uartclk = ssp->clkin_rate;
 	__ssp_update_div(ssp);
 
 	platform_set_drvdata(pdev, ssp);