Patch "x86/platform/uv: Update TSC sync state for UV5" has been added to the 5.17-stable tree

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This is a note to let you know that I've just added the patch titled

    x86/platform/uv: Update TSC sync state for UV5

to the 5.17-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     x86-platform-uv-update-tsc-sync-state-for-uv5.patch
and it can be found in the queue-5.17 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 9603c9cccda4c9d9fdaba63f873b8c57804d4c9a
Author: Mike Travis <mike.travis@xxxxxxx>
Date:   Wed Apr 6 14:51:48 2022 -0500

    x86/platform/uv: Update TSC sync state for UV5
    
    [ Upstream commit bb3ab81bdbd53f88f26ffabc9fb15bd8466486ec ]
    
    The UV5 platform synchronizes the TSCs among all chassis, and will not
    proceed to OS boot without achieving synchronization.  Previous UV
    platforms provided a register indicating successful synchronization.
    This is no longer available on UV5.  On this platform TSC_ADJUST
    should not be reset by the kernel.
    
    Signed-off-by: Mike Travis <mike.travis@xxxxxxx>
    Signed-off-by: Steve Wahl <steve.wahl@xxxxxxx>
    Signed-off-by: Borislav Petkov <bp@xxxxxxx>
    Reviewed-by: Dimitri Sivanich <dimitri.sivanich@xxxxxxx>
    Acked-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20220406195149.228164-3-steve.wahl@xxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index f5a48e66e4f5..a6e9c2794ef5 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -199,7 +199,13 @@ static void __init uv_tsc_check_sync(void)
 	int mmr_shift;
 	char *state;
 
-	/* Different returns from different UV BIOS versions */
+	/* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */
+	if (!is_uv(UV2|UV3|UV4)) {
+		mark_tsc_async_resets("UV5+");
+		return;
+	}
+
+	/* UV2,3,4, UV BIOS TSC sync state available */
 	mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
 	mmr_shift =
 		is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;



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