Patch "cxl/pci: Add debug for DVSEC range init failures" has been added to the 5.18-stable tree

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This is a note to let you know that I've just added the patch titled

    cxl/pci: Add debug for DVSEC range init failures

to the 5.18-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     cxl-pci-add-debug-for-dvsec-range-init-failures.patch
and it can be found in the queue-5.18 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit e734abaee8a1a784200618c9eaf958b7afe4464e
Author: Dan Williams <dan.j.williams@xxxxxxxxx>
Date:   Mon Mar 14 18:22:28 2022 -0700

    cxl/pci: Add debug for DVSEC range init failures
    
    [ Upstream commit e39f9be08d9dfe685c8a325ac1755c04f383effc ]
    
    In preparation for not treating DVSEC range initialization failures as
    fatal to cxl_pci_probe() add individual dev_dbg() statements for each of
    the major failure reasons in cxl_dvsec_ranges().
    
    The rationale for cxl_dvsec_ranges() failure not being fatal is that
    there is still value for cxl_pci to enable mailbox operations even if
    CXL.mem operation is disabled.
    
    Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
    Reviewed-by: Ben Widawsky <ben.widawsky@xxxxxxxxx>
    Reviewed-by: Davidlohr Bueso <dave@xxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/164730734812.3806189.2726330688692684104.stgit@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
    Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 3f2182d66829..c4941a3ca6a8 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -466,12 +466,15 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds)
 {
 	struct cxl_endpoint_dvsec_info *info = &cxlds->info;
 	struct pci_dev *pdev = to_pci_dev(cxlds->dev);
+	struct device *dev = &pdev->dev;
 	int d = cxlds->cxl_dvsec;
 	int hdm_count, rc, i;
 	u16 cap, ctrl;
 
-	if (!d)
+	if (!d) {
+		dev_dbg(dev, "No DVSEC Capability\n");
 		return -ENXIO;
+	}
 
 	rc = pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap);
 	if (rc)
@@ -481,8 +484,10 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds)
 	if (rc)
 		return rc;
 
-	if (!(cap & CXL_DVSEC_MEM_CAPABLE))
+	if (!(cap & CXL_DVSEC_MEM_CAPABLE)) {
+		dev_dbg(dev, "Not MEM Capable\n");
 		return -ENXIO;
+	}
 
 	/*
 	 * It is not allowed by spec for MEM.capable to be set and have 0 legacy
@@ -495,8 +500,10 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds)
 		return -EINVAL;
 
 	rc = wait_for_valid(cxlds);
-	if (rc)
+	if (rc) {
+		dev_dbg(dev, "Failure awaiting MEM_INFO_VALID (%d)\n", rc);
 		return rc;
+	}
 
 	info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl);
 



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