Patch "perf regs x86: Fix arch__intr_reg_mask() for the hybrid platform" has been added to the 5.15-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    perf regs x86: Fix arch__intr_reg_mask() for the hybrid platform

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     perf-regs-x86-fix-arch__intr_reg_mask-for-the-hybrid.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 175d9d52560d47afb326cfbd3418cfd3dbb1cffb
Author: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
Date:   Wed May 18 07:51:25 2022 -0700

    perf regs x86: Fix arch__intr_reg_mask() for the hybrid platform
    
    [ Upstream commit 01b28e4a58152e8906eeb5f1b55a0c404c48c7c8 ]
    
    The X86 specific arch__intr_reg_mask() is to check whether the kernel
    and hardware can collect XMM registers. But it doesn't work on some
    hybrid platform.
    
    Without the patch on ADL-N:
    
      $ perf record -I?
      available registers: AX BX CX DX SI DI BP SP IP FLAGS CS SS R8 R9 R10
      R11 R12 R13 R14 R15
    
    The config of the test event doesn't contain the PMU information. The
    kernel may fail to initialize it on the correct hybrid PMU and return
    the wrong non-supported information.
    
    Add the PMU information into the config for the hybrid platform. The
    same register set is supported among different hybrid PMUs. Checking
    the first available one is good enough.
    
    With the patch on ADL-N:
    
      $ perf record -I?
      available registers: AX BX CX DX SI DI BP SP IP FLAGS CS SS R8 R9 R10
      R11 R12 R13 R14 R15 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9
      XMM10 XMM11 XMM12 XMM13 XMM14 XMM15
    
    Fixes: 6466ec14aaf44ff1 ("perf regs x86: Add X86 specific arch__intr_reg_mask()")
    Reported-by: Ammy Yi <ammy.yi@xxxxxxxxx>
    Signed-off-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
    Acked-by: Ian Rogers <irogers@xxxxxxxxxx>
    Cc: Ingo Molnar <mingo@xxxxxxxxxx>
    Cc: Jiri Olsa <jolsa@xxxxxxxxxx>
    Cc: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
    Cc: Namhyung Kim <namhyung@xxxxxxxxxx>
    Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
    Cc: Xing Zhengjun <zhengjun.xing@xxxxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20220518145125.1494156-1-kan.liang@xxxxxxxxxxxxxxx
    Signed-off-by: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/tools/perf/arch/x86/util/perf_regs.c b/tools/perf/arch/x86/util/perf_regs.c
index 207c56805c55..0ed177991ad0 100644
--- a/tools/perf/arch/x86/util/perf_regs.c
+++ b/tools/perf/arch/x86/util/perf_regs.c
@@ -9,6 +9,8 @@
 #include "../../../util/perf_regs.h"
 #include "../../../util/debug.h"
 #include "../../../util/event.h"
+#include "../../../util/pmu.h"
+#include "../../../util/pmu-hybrid.h"
 
 const struct sample_reg sample_reg_masks[] = {
 	SMPL_REG(AX, PERF_REG_X86_AX),
@@ -284,12 +286,22 @@ uint64_t arch__intr_reg_mask(void)
 		.disabled 		= 1,
 		.exclude_kernel		= 1,
 	};
+	struct perf_pmu *pmu;
 	int fd;
 	/*
 	 * In an unnamed union, init it here to build on older gcc versions
 	 */
 	attr.sample_period = 1;
 
+	if (perf_pmu__has_hybrid()) {
+		/*
+		 * The same register set is supported among different hybrid PMUs.
+		 * Only check the first available one.
+		 */
+		pmu = list_first_entry(&perf_pmu__hybrid_pmus, typeof(*pmu), hybrid_list);
+		attr.config |= (__u64)pmu->type << PERF_PMU_TYPE_SHIFT;
+	}
+
 	event_attr_init(&attr);
 
 	fd = sys_perf_event_open(&attr, 0, -1, -1, 0);