Patch "scsi: pm80xx: Mask and unmask upper interrupt vectors 32-63" has been added to the 5.17-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    scsi: pm80xx: Mask and unmask upper interrupt vectors 32-63

to the 5.17-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     scsi-pm80xx-mask-and-unmask-upper-interrupt-vectors-.patch
and it can be found in the queue-5.17 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit b7a1b801ab1c9b1fac3b62d22366e6f418235a14
Author: Ajish Koshy <Ajish.Koshy@xxxxxxxxxxxxx>
Date:   Mon Apr 11 12:16:02 2022 +0530

    scsi: pm80xx: Mask and unmask upper interrupt vectors 32-63
    
    [ Upstream commit 294080eacf92a0781e6d43663448a55001ec8c64 ]
    
    When upper inbound and outbound queues 32-63 are enabled, we see upper
    vectors 32-63 in interrupt service routine. We need corresponding registers
    to handle masking and unmasking of these upper interrupts.
    
    To achieve this, we use registers MSGU_ODMR_U(0x34) to mask and
    MSGU_ODMR_CLR_U(0x3C) to unmask the interrupts. In these registers bit 0-31
    represents interrupt vectors 32-63.
    
    Link: https://lore.kernel.org/r/20220411064603.668448-2-Ajish.Koshy@xxxxxxxxxxxxx
    Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues")
    Reviewed-by: John Garry <john.garry@xxxxxxxxxx>
    Acked-by: Jack Wang <jinpu.wang@xxxxxxxxx>
    Signed-off-by: Ajish Koshy <Ajish.Koshy@xxxxxxxxxxxxx>
    Signed-off-by: Viswas G <Viswas.G@xxxxxxxxxxxxx>
    Signed-off-by: Martin K. Petersen <martin.petersen@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
index 55163469030d..2dea48933ef9 100644
--- a/drivers/scsi/pm8001/pm80xx_hwi.c
+++ b/drivers/scsi/pm8001/pm80xx_hwi.c
@@ -1734,10 +1734,11 @@ static void
 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
 {
 #ifdef PM8001_USE_MSIX
-	u32 mask;
-	mask = (u32)(1 << vec);
-
-	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
+	if (vec < 32)
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
+	else
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
+			    1U << (vec - 32));
 	return;
 #endif
 	pm80xx_chip_intx_interrupt_enable(pm8001_ha);
@@ -1753,12 +1754,15 @@ static void
 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
 {
 #ifdef PM8001_USE_MSIX
-	u32 mask;
-	if (vec == 0xFF)
-		mask = 0xFFFFFFFF;
+	if (vec == 0xFF) {
+		/* disable all vectors 0-31, 32-63 */
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
+	} else if (vec < 32)
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
 	else
-		mask = (u32)(1 << vec);
-	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
+			    1U << (vec - 32));
 	return;
 #endif
 	pm80xx_chip_intx_interrupt_disable(pm8001_ha);