From: Suzuki K Poulose <suzuki.poulose@xxxxxxx> [ Upstream commit be5b299830c63ed76e0357473c4218c85fb388b3 ] Add helpers for detecting an errata on list of midr ranges of affected CPUs, with the same work around. Cc: Will Deacon <will.deacon@xxxxxxx> Cc: Mark Rutland <mark.rutland@xxxxxxx> Cc: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Reviewed-by: Dave Martin <dave.martin@xxxxxxx> Signed-off-by: Suzuki K Poulose <suzuki.poulose@xxxxxxx> Signed-off-by: Will Deacon <will.deacon@xxxxxxx> [ardb: add Cortex-A35 to kpti_safe_list[] as well] Signed-off-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> Signed-off-by: James Morse <james.morse@xxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/arm64/include/asm/cpufeature.h | 1 arch/arm64/include/asm/cputype.h | 9 +++++ arch/arm64/kernel/cpu_errata.c | 62 ++++++++++++++++++++---------------- arch/arm64/kernel/cpufeature.c | 21 ++++++------ 4 files changed, 58 insertions(+), 35 deletions(-) --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -233,6 +233,7 @@ struct arm64_cpu_capabilities { struct midr_range midr_range; }; + const struct midr_range *midr_range_list; struct { /* Feature register checking */ u32 sys_reg; u8 field_pos; --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -143,6 +143,15 @@ static inline bool is_midr_in_range(u32 range->rv_min, range->rv_max); } +static inline bool +is_midr_in_range_list(u32 midr, struct midr_range const *ranges) +{ + while (ranges->model) + if (is_midr_in_range(midr, ranges++)) + return true; + return false; +} + /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -33,6 +33,14 @@ is_affected_midr_range(const struct arm6 return is_midr_in_range(midr, &entry->midr_range); } +static bool __maybe_unused +is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, + int scope) +{ + WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); + return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); +} + static bool has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, int scope) @@ -383,6 +391,10 @@ static bool has_ssbd_mitigation(const st .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) +#define CAP_MIDR_RANGE_LIST(list) \ + .matches = is_affected_midr_range_list, \ + .midr_range_list = list + /* Errata affecting a range of revisions of given model variant */ #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) @@ -396,6 +408,29 @@ static bool has_ssbd_mitigation(const st .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ CAP_MIDR_ALL_VERSIONS(model) +/* Errata affecting a list of midr ranges, with same work around */ +#define ERRATA_MIDR_RANGE_LIST(midr_list) \ + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ + CAP_MIDR_RANGE_LIST(midr_list) + +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + +/* + * List of CPUs where we need to issue a psci call to + * harden the branch predictor. + */ +static const struct midr_range arm64_bp_harden_smccc_cpus[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), + {}, +}; + +#endif + const struct arm64_cpu_capabilities arm64_errata[] = { #if defined(CONFIG_ARM64_ERRATUM_826319) || \ defined(CONFIG_ARM64_ERRATUM_827319) || \ @@ -486,32 +521,7 @@ const struct arm64_cpu_capabilities arm6 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .cpu_enable = enable_smccc_arch_workaround_1, - }, - { - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .cpu_enable = enable_smccc_arch_workaround_1, - }, - { - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .cpu_enable = enable_smccc_arch_workaround_1, - }, - { - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .cpu_enable = enable_smccc_arch_workaround_1, - }, - { - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - ERRATA_MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), - .cpu_enable = enable_smccc_arch_workaround_1, - }, - { - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - ERRATA_MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), + ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus), .cpu_enable = enable_smccc_arch_workaround_1, }, #endif --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -767,6 +767,17 @@ static int __kpti_forced; /* 0: not forc static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, int __unused) { + /* List of CPUs that are not vulnerable and don't need KPTI */ + static const struct midr_range kpti_safe_list[] = { + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + }; char const *str = "command line option"; u64 pfr0 = read_system_reg(SYS_ID_AA64PFR0_EL1); @@ -792,16 +803,8 @@ static bool unmap_kernel_at_el0(const st return true; /* Don't force KPTI for CPUs that are not vulnerable */ - switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) { - case MIDR_CAVIUM_THUNDERX2: - case MIDR_BRCM_VULCAN: - case MIDR_CORTEX_A53: - case MIDR_CORTEX_A55: - case MIDR_CORTEX_A57: - case MIDR_CORTEX_A72: - case MIDR_CORTEX_A73: + if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list)) return false; - } /* Defer to CPU feature registers */ return !cpuid_feature_extract_unsigned_field(pfr0, Patches currently in stable-queue which might be from james.morse@xxxxxxx are queue-4.9/clocksource-drivers-arm_arch_timer-remove-fsl-a008585-parameter.patch queue-4.9/arm64-capabilities-clean-up-midr-range-helpers.patch queue-4.9/arm64-entry-add-macro-for-reading-symbol-addresses-from-the-trampoline.patch queue-4.9/arm64-use-the-clearbhb-instruction-in-mitigations.patch queue-4.9/arm64-add-percpu-vectors-for-el1.patch queue-4.9/arm64-arch_timer-add-workaround-for-arm-erratum-1188873.patch queue-4.9/arm64-capabilities-add-support-for-checks-based-on-a-list-of-midrs.patch queue-4.9/arm64-arch_timer-add-infrastructure-for-multiple-erratum-detection-methods.patch queue-4.9/arm64-entry-free-up-another-register-on-kpti-s-tramp_exit-path.patch queue-4.9/arm64-entry-don-t-assume-tramp_vectors-is-the-start-of-the-vectors.patch queue-4.9/arm64-entry-make-the-trampoline-cleanup-optional.patch queue-4.9/arm64-add-silicon-errata.txt-entry-for-arm-erratum-1188873.patch queue-4.9/clocksource-drivers-arm_arch_timer-introduce-generic-errata-handling-infrastructure.patch queue-4.9/kvm-arm64-add-templates-for-bhb-mitigation-sequences.patch queue-4.9/arm64-entry-add-non-kpti-__bp_harden_el1_vectors-for-mitigations.patch queue-4.9/arm64-add-id_aa64isar2_el1-sys-register.patch queue-4.9/kvm-arm64-allow-smccc_arch_workaround_3-to-be-discovered-and-migrated.patch queue-4.9/arm64-capabilities-update-prototype-for-enable-call-back.patch queue-4.9/arm64-add-neoverse-n2-cortex-a710-cpu-part-definition.patch queue-4.9/arm64-add-midr-encoding-for-arm-cortex-a55-and-cortex-a35.patch queue-4.9/arm64-capabilities-move-errata-processing-code.patch queue-4.9/arm64-arch_timer-add-erratum-handler-for-cpu-specific-capability.patch queue-4.9/arm64-errata-provide-macro-for-major-and-minor-cpu-revisions.patch queue-4.9/arm64-arch_timer-avoid-unused-function-warning.patch queue-4.9/arm64-capabilities-move-errata-work-around-check-on-boot-cpu.patch queue-4.9/arm64-add-helpers-for-checking-cpu-midr-against-a-range.patch queue-4.9/arm64-entry-move-trampoline-macros-out-of-ifdef-d-section.patch queue-4.9/arm64-entry-allow-tramp_alias-to-access-symbols-after-the-4k-boundary.patch queue-4.9/arm64-add-part-number-for-arm-cortex-a77.patch queue-4.9/arm64-capabilities-add-flags-to-handle-the-conflicts-on-late-cpu.patch queue-4.9/arm64-entry-move-the-trampoline-data-page-before-the-text-page.patch queue-4.9/arm64-entry.s-add-ventry-overflow-sanity-checks.patch queue-4.9/arm64-add-part-number-for-neoverse-n1.patch queue-4.9/arm64-entry-add-vectors-that-have-the-bhb-mitigation-sequences.patch queue-4.9/arm64-make-arm64_erratum_1188873-depend-on-compat.patch queue-4.9/arm64-mitigate-spectre-style-branch-history-side-channels.patch queue-4.9/arm64-move-arm64_update_smccc_conduit-out-of-ssbd-ifdef.patch queue-4.9/arm64-entry-allow-the-trampoline-text-to-occupy-multiple-pages.patch queue-4.9/arm64-add-cortex-x2-cpu-part-definition.patch queue-4.9/arm64-add-helper-to-decode-register-from-instruction.patch queue-4.9/arm64-capabilities-prepare-for-fine-grained-capabilities.patch queue-4.9/arm64-remove-useless-uao-ipi-and-describe-how-this-gets-enabled.patch queue-4.9/arm64-entry-make-the-kpti-trampoline-s-kpti-sequence-optional.patch