Patch "clk: qcom: clk-rcg2: Update logic to calculate D value for RCG" has been added to the 5.15-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    clk: qcom: clk-rcg2: Update logic to calculate D value for RCG

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-clk-rcg2-update-logic-to-calculate-d-value-.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 8184733df360339d040d9f5943e4ce31e0a934e7
Author: Taniya Das <tdas@xxxxxxxxxxxxxx>
Date:   Sun Feb 27 23:25:35 2022 +0530

    clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
    
    [ Upstream commit 58922910add18583d5273c2edcdb9fd7bf4eca02 ]
    
    The display pixel clock has a requirement on certain newer platforms to
    support M/N as (2/3) and the final D value calculated results in
    underflow errors.
    As the current implementation does not check for D value is within
    the accepted range for a given M & N value. Update the logic to
    calculate the final D value based on the range.
    
    Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks")
    Signed-off-by: Taniya Das <tdas@xxxxxxxxxxxxxx>
    Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20220227175536.3131-1-tdas@xxxxxxxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index e1b1b426fae4..b831975a9606 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
 
 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 {
-	u32 cfg, mask;
+	u32 cfg, mask, d_val, not2d_val, n_minus_m;
 	struct clk_hw *hw = &rcg->clkr.hw;
 	int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
 
@@ -283,8 +283,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 		if (ret)
 			return ret;
 
+		/* Calculate 2d value */
+		d_val = f->n;
+
+		n_minus_m = f->n - f->m;
+		n_minus_m *= 2;
+
+		d_val = clamp_t(u32, d_val, f->m, n_minus_m);
+		not2d_val = ~d_val & mask;
+
 		ret = regmap_update_bits(rcg->clkr.regmap,
-				RCG_D_OFFSET(rcg), mask, ~f->n);
+				RCG_D_OFFSET(rcg), mask, not2d_val);
 		if (ret)
 			return ret;
 	}