Patch "serial: 8250_aspeed_vuart: add PORT_ASPEED_VUART port type" has been added to the 5.15-stable tree

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This is a note to let you know that I've just added the patch titled

    serial: 8250_aspeed_vuart: add PORT_ASPEED_VUART port type

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     serial-8250_aspeed_vuart-add-port_aspeed_vuart-port-.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit acb91ebd07d542721b85d37cc3f8871f452c56f7
Author: Zev Weiss <zev@xxxxxxxxxxxxxxxxx>
Date:   Thu Feb 10 16:42:03 2022 -0800

    serial: 8250_aspeed_vuart: add PORT_ASPEED_VUART port type
    
    [ Upstream commit a603ca60cebff8589882427a67f870ed946b3fc8 ]
    
    Commit 54da3e381c2b ("serial: 8250_aspeed_vuart: use UPF_IOREMAP to
    set up register mapping") fixed a bug that had, as a side-effect,
    prevented the 8250_aspeed_vuart driver from enabling the VUART's
    FIFOs.  However, fixing that (and hence enabling the FIFOs) has in
    turn revealed what appears to be a hardware bug in the ASPEED VUART in
    which the host-side THRE bit doesn't get if the BMC-side receive FIFO
    trigger level is set to anything but one byte.  This causes problems
    for polled-mode writes from the host -- for example, Linux kernel
    console writes proceed at a glacial pace (less than 100 bytes per
    second) because the write path waits for a 10ms timeout to expire
    after every character instead of being able to continue on to the next
    character upon seeing THRE asserted.  (GRUB behaves similarly.)
    
    As a workaround, introduce a new port type for the ASPEED VUART that's
    identical to PORT_16550A as it had previously been using, but with
    UART_FCR_R_TRIG_00 instead to set the receive FIFO trigger level to
    one byte, which (experimentally) seems to avoid the problematic THRE
    behavior.
    
    Fixes: 54da3e381c2b ("serial: 8250_aspeed_vuart: use UPF_IOREMAP to set up register mapping")
    Tested-by: Konstantin Aladyshev <aladyshev22@xxxxxxxxx>
    Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
    Signed-off-by: Zev Weiss <zev@xxxxxxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20220211004203.14915-1-zev@xxxxxxxxxxxxxxxxx
    Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/serial/8250/8250_aspeed_vuart.c
index 2350fb3bb5e4..c2cecc6f47db 100644
--- a/drivers/tty/serial/8250/8250_aspeed_vuart.c
+++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c
@@ -487,7 +487,7 @@ static int aspeed_vuart_probe(struct platform_device *pdev)
 	port.port.irq = irq_of_parse_and_map(np, 0);
 	port.port.handle_irq = aspeed_vuart_handle_irq;
 	port.port.iotype = UPIO_MEM;
-	port.port.type = PORT_16550A;
+	port.port.type = PORT_ASPEED_VUART;
 	port.port.uartclk = clk;
 	port.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
 		| UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_NO_THRE_TEST;
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index ec88b706e882..b470bc747b99 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -307,6 +307,14 @@ static const struct serial8250_config uart_config[] = {
 		.rxtrig_bytes	= {1, 32, 64, 112},
 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
 	},
+	[PORT_ASPEED_VUART] = {
+		.name		= "ASPEED VUART",
+		.fifo_size	= 16,
+		.tx_loadsz	= 16,
+		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
+		.rxtrig_bytes	= {1, 4, 8, 14},
+		.flags		= UART_CAP_FIFO,
+	},
 };
 
 /* Uart divisor latch read */
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index c4042dcfdc0c..8885e69178bd 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -68,6 +68,9 @@
 /* NVIDIA Tegra Combined UART */
 #define PORT_TEGRA_TCU	41
 
+/* ASPEED AST2x00 virtual UART */
+#define PORT_ASPEED_VUART	42
+
 /* Intel EG20 */
 #define PORT_PCH_8LINE	44
 #define PORT_PCH_2LINE	45



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