This is a note to let you know that I've just added the patch titled
MIPS: Sanitise Cavium switch cases in TLB handler synthesizers
to the 5.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-sanitise-cavium-switch-cases-in-tlb-handler-syn.patch
and it can be found in the queue-5.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit a48a954ce993d1c93d716f62b4994a35612a4b0d
Author: Maciej W. Rozycki <macro@xxxxxxxxxxx>
Date: Fri Mar 4 21:13:11 2022 +0000
MIPS: Sanitise Cavium switch cases in TLB handler synthesizers
[ Upstream commit 6ddcba9d480b6bcced4223a729794dfa6becb7eb ]
It makes no sense to fall through to `break'. Therefore reorder the
switch statements so as to have the Cavium cases first, followed by the
default case, which improves readability and pacifies code analysis
tools. No change in semantics, assembly produced is exactly the same.
Reported-by: kernel test robot <lkp@xxxxxxxxx>
Signed-off-by: Maciej W. Rozycki <macro@xxxxxxxxxxx>
Fixes: bc431d2153cc ("MIPS: Fix fall-through warnings for Clang")
Signed-off-by: Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 9adad24c2e65..046d51a454af 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2167,16 +2167,14 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
switch (current_cpu_type()) {
- default:
- if (cpu_has_mips_r2_exec_hazard) {
- uasm_i_ehb(&p);
- fallthrough;
-
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
- break;
- }
+ break;
+ default:
+ if (cpu_has_mips_r2_exec_hazard)
+ uasm_i_ehb(&p);
+ break;
}
/* Examine entrylo 0 or 1 based on ptr. */
@@ -2243,15 +2241,14 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
switch (current_cpu_type()) {
- default:
- if (cpu_has_mips_r2_exec_hazard) {
- uasm_i_ehb(&p);
-
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
- break;
- }
+ break;
+ default:
+ if (cpu_has_mips_r2_exec_hazard)
+ uasm_i_ehb(&p);
+ break;
}
/* Examine entrylo 0 or 1 based on ptr. */
