From: Nishanth Menon <nm@xxxxxx> commit a966803781fc5e1875511db9392b0d16174c5dd2 upstream. Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@xxxxxxxxxx/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@xxxxxxxxxxxxxxx Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Reported-by: Marc Zyngier <maz@xxxxxxxxxx> Signed-off-by: Nishanth Menon <nm@xxxxxx> Acked-by: Marc Zyngier <maz@xxxxxxxxxx> Link: https://lore.kernel.org/r/20220215201008.15235-6-nm@xxxxxx Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 5 ++++- arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -34,7 +34,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -119,6 +119,7 @@ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ Patches currently in stable-queue which might be from nm@xxxxxx are queue-5.17/arm64-dts-ti-k3-j721e-fix-gic-v3-compatible-regs.patch queue-5.17/arm64-dts-ti-k3-j7200-fix-gic-v3-compatible-regs.patch queue-5.17/arm64-dts-ti-k3-am64-fix-gic-v3-compatible-regs.patch queue-5.17/arm64-dts-ti-k3-j721s2-fix-gic-v3-compatible-regs.patch queue-5.17/arm64-dts-ti-k3-am65-fix-gic-v3-compatible-regs.patch