Patch "arm64: Add Neoverse-N2, Cortex-A710 CPU part definition" has been added to the 5.4-stable tree

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This is a note to let you know that I've just added the patch titled

    arm64: Add Neoverse-N2, Cortex-A710 CPU part definition

to the 5.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-add-neoverse-n2-cortex-a710-cpu-part-definitio.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit faf8122f60a82f1c0557706a02e219c3e08e492a
Author: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
Date:   Tue Mar 15 18:23:55 2022 +0000

    arm64: Add Neoverse-N2, Cortex-A710 CPU part definition
    
    commit 2d0d656700d67239a57afaf617439143d8dac9be upstream.
    
    Add the CPU Partnumbers for the new Arm designs.
    
    Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
    Cc: Mark Rutland <mark.rutland@xxxxxxx>
    Cc: Will Deacon <will@xxxxxxxxxx>
    Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx>
    Reviewed-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
    Signed-off-by: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
    Link: https://lore.kernel.org/r/20211019163153.3692640-2-suzuki.poulose@xxxxxxx
    Signed-off-by: Will Deacon <will@xxxxxxxxxx>
    Signed-off-by: James Morse <james.morse@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index b009d4813537..6a0acbec77ae 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -72,6 +72,8 @@
 #define ARM_CPU_PART_CORTEX_A76		0xD0B
 #define ARM_CPU_PART_NEOVERSE_N1	0xD0C
 #define ARM_CPU_PART_CORTEX_A77		0xD0D
+#define ARM_CPU_PART_CORTEX_A710	0xD47
+#define ARM_CPU_PART_NEOVERSE_N2	0xD49
 
 #define APM_CPU_PART_POTENZA		0x000
 
@@ -104,6 +106,8 @@
 #define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
 #define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
+#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
+#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)



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