From: Tony Luck <tony.luck@xxxxxxxxx> commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream. New CPU model, same MSRs to control and read the inventory number. Signed-off-by: Tony Luck <tony.luck@xxxxxxxxx> Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx> Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@xxxxxxxxx Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/x86/kernel/cpu/mce/intel.c | 1 + 1 file changed, 1 insertion(+) --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuin case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: case INTEL_FAM6_ICELAKE_X: + case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: Patches currently in stable-queue which might be from tony.luck@xxxxxxxxx are queue-5.10/x86-cpu-add-xeon-icelake-d-to-list-of-cpus-that-support-ppin.patch queue-5.10/x86-mce-add-xeon-sapphire-rapids-to-list-of-cpus-that-support-ppin.patch