This is a note to let you know that I've just added the patch titled
net: axienet: reset core on initialization prior to MDIO access
to the 5.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
net-axienet-reset-core-on-initialization-prior-to-mdio-access.patch
and it can be found in the queue-5.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 04cc2da39698efd7eb2e30c112538922d26f848e Mon Sep 17 00:00:00 2001
From: Robert Hancock <robert.hancock@xxxxxxxxxx>
Date: Tue, 18 Jan 2022 15:41:26 -0600
Subject: net: axienet: reset core on initialization prior to MDIO access
From: Robert Hancock <robert.hancock@xxxxxxxxxx>
commit 04cc2da39698efd7eb2e30c112538922d26f848e upstream.
In some cases where the Xilinx Ethernet core was used in 1000Base-X or
SGMII modes, which use the internal PCS/PMA PHY, and the MGT
transceiver clock source for the PCS was not running at the time the
FPGA logic was loaded, the core would come up in a state where the
PCS could not be found on the MDIO bus. To fix this, the Ethernet core
(including the PCS) should be reset after enabling the clocks, prior to
attempting to access the PCS using of_mdio_find_device.
Fixes: 1a02556086fc (net: axienet: Properly handle PCS/PMA PHY for 1000BaseX mode)
Signed-off-by: Robert Hancock <robert.hancock@xxxxxxxxxx>
Reviewed-by: Andrew Lunn <andrew@xxxxxxx>
Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 5 +++++
1 file changed, 5 insertions(+)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -2024,6 +2024,11 @@ static int axienet_probe(struct platform
lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
+ /* Reset core now that clocks are enabled, prior to accessing MDIO */
+ ret = __axienet_device_reset(lp);
+ if (ret)
+ goto cleanup_clk;
+
lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
if (lp->phy_node) {
ret = axienet_mdio_setup(lp);
Patches currently in stable-queue which might be from robert.hancock@xxxxxxxxxx are
queue-5.10/net-axienet-wait-for-phyrstcmplt-after-core-reset.patch
queue-5.10/net-axienet-add-missing-memory-barriers.patch
queue-5.10/clk-si5341-fix-clock-hw-provider-cleanup.patch
queue-5.10/net-axienet-increase-default-tx-ring-size-to-128.patch
queue-5.10/net-axienet-fix-tx-ring-slot-available-check.patch
queue-5.10/net-axienet-fix-for-tx-busy-handling.patch
queue-5.10/net-axienet-limit-minimum-tx-ring-size.patch
queue-5.10/net-axienet-reset-core-on-initialization-prior-to-mdio-access.patch
queue-5.10/net-axienet-fix-number-of-tx-ring-slots-for-available-check.patch
queue-5.10/net-axienet-increase-reset-timeout.patch
