This is a note to let you know that I've just added the patch titled PCI: pci-bridge-emul: Fix definitions of reserved bits to the 5.16-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: pci-pci-bridge-emul-fix-definitions-of-reserved-bits.patch and it can be found in the queue-5.16 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From 12998087d9f48b66965b97412069c7826502cd7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@xxxxxxxxxx> Date: Wed, 24 Nov 2021 16:59:42 +0100 Subject: PCI: pci-bridge-emul: Fix definitions of reserved bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Pali Rohár <pali@xxxxxxxxxx> commit 12998087d9f48b66965b97412069c7826502cd7e upstream. Some bits in PCI_EXP registers are reserved for non-root ports. Driver pci-bridge-emul.c implements PCIe Root Port device therefore it should not allow setting reserved bits of registers. Properly define non-reserved bits for all PCI_EXP registers. Link: https://lore.kernel.org/r/20211124155944.1290-5-pali@xxxxxxxxxx Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic") Signed-off-by: Pali Rohár <pali@xxxxxxxxxx> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> Cc: stable@xxxxxxxxxxxxxxx Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/pci/pci-bridge-emul.c | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) --- a/drivers/pci/pci-bridge-emul.c +++ b/drivers/pci/pci-bridge-emul.c @@ -176,41 +176,55 @@ struct pci_bridge_reg_behavior pcie_cap_ [PCI_CAP_LIST_ID / 4] = { /* * Capability ID, Next Capability Pointer and - * Capabilities register are all read-only. + * bits [14:0] of Capabilities register are all read-only. + * Bit 15 of Capabilities register is reserved. */ - .ro = ~0, + .ro = GENMASK(30, 0), }, [PCI_EXP_DEVCAP / 4] = { - .ro = ~0, + /* + * Bits [31:29] and [17:16] are reserved. + * Bits [27:18] are reserved for non-upstream ports. + * Bits 28 and [14:6] are reserved for non-endpoint devices. + * Other bits are read-only. + */ + .ro = BIT(15) | GENMASK(5, 0), }, [PCI_EXP_DEVCTL / 4] = { - /* Device control register is RW */ - .rw = GENMASK(15, 0), + /* + * Device control register is RW, except bit 15 which is + * reserved for non-endpoints or non-PCIe-to-PCI/X bridges. + */ + .rw = GENMASK(14, 0), /* * Device status register has bits 6 and [3:0] W1C, [5:4] RO, - * the rest is reserved + * the rest is reserved. Also bit 6 is reserved for non-upstream + * ports. */ - .w1c = (BIT(6) | GENMASK(3, 0)) << 16, + .w1c = GENMASK(3, 0) << 16, .ro = GENMASK(5, 4) << 16, }, [PCI_EXP_LNKCAP / 4] = { - /* All bits are RO, except bit 23 which is reserved */ - .ro = lower_32_bits(~BIT(23)), + /* + * All bits are RO, except bit 23 which is reserved and + * bit 18 which is reserved for non-upstream ports. + */ + .ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)), }, [PCI_EXP_LNKCTL / 4] = { /* * Link control has bits [15:14], [11:3] and [1:0] RW, the - * rest is reserved. + * rest is reserved. Bit 8 is reserved for non-upstream ports. * * Link status has bits [13:0] RO, and bits [15:14] * W1C. */ - .rw = GENMASK(15, 14) | GENMASK(11, 3) | GENMASK(1, 0), + .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0), .ro = GENMASK(13, 0) << 16, .w1c = GENMASK(15, 14) << 16, }, Patches currently in stable-queue which might be from pali@xxxxxxxxxx are queue-5.16/pci-pci-bridge-emul-make-expansion-rom-base-address-register-read-only.patch queue-5.16/pci-mvebu-fix-support-for-pci_bridge_ctl_bus_reset-o.patch queue-5.16/pci-pci-bridge-emul-fix-definitions-of-reserved-bits.patch queue-5.16/pci-mvebu-setup-pcie-controller-to-root-complex-mode.patch queue-5.16/pci-pci-bridge-emul-correctly-set-pcie-capabilities.patch queue-5.16/pci-mvebu-fix-support-for-pci_exp_devctl-on-emulated.patch queue-5.16/pci-mvebu-do-not-modify-pci-io-type-bits-in-conf_wri.patch queue-5.16/pci-mvebu-check-for-errors-from-pci_bridge_emul_init.patch queue-5.16/pci-pci-bridge-emul-properly-mark-reserved-pcie-bits-in-pci-config-space.patch queue-5.16/pci-pci-bridge-emul-set-pci_status_cap_list-for-pcie-device.patch queue-5.16/pci-aardvark-fix-checking-for-mem-resource-type.patch queue-5.16/arm-dts-armada-38x-add-generic-compatible-to-uart-no.patch queue-5.16/pci-mvebu-fix-configuring-secondary-bus-of-pcie-root.patch queue-5.16/pci-mvebu-fix-support-for-pci_exp_rtsta-on-emulated-.patch queue-5.16/pci-mvebu-fix-support-for-bus-mastering-and-pci_comm.patch queue-5.16/pci-mvebu-fix-support-for-devcap2-devctl2-and-lnkctl.patch