This is a note to let you know that I've just added the patch titled
arm64: tegra: Fix Tegra194 HDA {clock,reset}-names ordering
to the 5.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-tegra-fix-tegra194-hda-clock-reset-names-order.patch
and it can be found in the queue-5.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit bf9222167401a87bf57f372608e74a9a75450331
Author: Sameer Pujar <spujar@xxxxxxxxxx>
Date: Wed Nov 18 13:36:20 2020 +0530
arm64: tegra: Fix Tegra194 HDA {clock,reset}-names ordering
[ Upstream commit 48f6e195039486bc303118948f49a9873acc888f ]
As per the HDA binding doc reorder {clock,reset}-names entries for
Tegra194. This also serves as a preparation for converting existing
binding doc to json-schema.
Signed-off-by: Sameer Pujar <spujar@xxxxxxxxxx>
Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 9b5007e5f790f..815df654e6387 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -782,13 +782,13 @@ hda@3510000 {
reg = <0x3510000 0x10000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_HDA>,
- <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
- <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
- clock-names = "hda", "hda2codec_2x", "hda2hdmi";
+ <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
+ <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
+ clock-names = "hda", "hda2hdmi", "hda2codec_2x";
resets = <&bpmp TEGRA194_RESET_HDA>,
- <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
- <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
- reset-names = "hda", "hda2codec_2x", "hda2hdmi";
+ <&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
+ <&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
+ reset-names = "hda", "hda2hdmi", "hda2codec_2x";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
