Patch "drm/amdgpu/gfx10: add wraparound gpu counter check for APUs as well" has been added to the 5.15-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/amdgpu/gfx10: add wraparound gpu counter check for APUs as well

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amdgpu-gfx10-add-wraparound-gpu-counter-check-for-apus-as-well.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.


>From 244ee398855df2adc7d3ac5702b58424a5f684cc Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Thu, 18 Nov 2021 14:33:23 -0500
Subject: drm/amdgpu/gfx10: add wraparound gpu counter check for APUs as well

From: Alex Deucher <alexander.deucher@xxxxxxx>

commit 244ee398855df2adc7d3ac5702b58424a5f684cc upstream.

Apply the same check we do for dGPUs for APUs as well.

Acked-by: Luben Tuikov <luben.tuikov@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |   15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7729,8 +7729,19 @@ static uint64_t gfx_v10_0_get_gpu_clock_
 	switch (adev->asic_type) {
 	case CHIP_VANGOGH:
 	case CHIP_YELLOW_CARP:
-		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
-			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
+		preempt_disable();
+		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
+		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
+		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
+		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
+		 * roughly every 42 seconds.
+		 */
+		if (hi_check != clock_hi) {
+			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
+			clock_hi = hi_check;
+		}
+		preempt_enable();
+		clock = clock_lo | (clock_hi << 32ULL);
 		break;
 	default:
 		preempt_disable();


Patches currently in stable-queue which might be from alexander.deucher@xxxxxxx are

queue-5.15/drm-amd-display-fix-dpia-outbox-timeout-after-gpu-re.patch
queue-5.15/drm-amdgpu-ih-process-reset-count-when-restart.patch
queue-5.15/drm-amd-display-fix-oled-brightness-control-on-edp.patch
queue-5.15/drm-amdgpu-gfx10-add-wraparound-gpu-counter-check-for-apus-as-well.patch
queue-5.15/drm-amdgpu-pm-fix-powerplay-od-interface.patch
queue-5.15/drm-amd-display-set-plane-update-flags-for-all-plane.patch
queue-5.15/drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch



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