This is a note to let you know that I've just added the patch titled PCI: aardvark: Replace custom macros by standard linux/pci_regs.h macros to the 4.14-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: pci-aardvark-replace-custom-macros-by-standard-linux-pci_regs.h-macros.patch and it can be found in the queue-4.14 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From foo@baz Mon Nov 29 01:32:04 PM CET 2021 From: "Marek Behún" <kabel@xxxxxxxxxx> Date: Wed, 24 Nov 2021 23:49:16 +0100 Subject: PCI: aardvark: Replace custom macros by standard linux/pci_regs.h macros To: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>, Sasha Levin <sashal@xxxxxxxxxx> Cc: pali@xxxxxxxxxx, stable@xxxxxxxxxxxxxxx, "Tomasz Maciej Nowak" <tmn505@xxxxxxxxx>, "Lorenzo Pieralisi" <lorenzo.pieralisi@xxxxxxx>, "Rob Herring" <robh@xxxxxxxxxx>, "Thomas Petazzoni" <thomas.petazzoni@xxxxxxxxxxx>, "Marek Behún" <kabel@xxxxxxxxxx> Message-ID: <20211124224933.24275-8-kabel@xxxxxxxxxx> From: Pali Rohár <pali@xxxxxxxxxx> commit 96be36dbffacea0aa9e6ec4839583e79faa141a1 upstream. PCI-E capability macros are already defined in linux/pci_regs.h. Remove their reimplementation in pcie-aardvark. Link: https://lore.kernel.org/r/20200430080625.26070-9-pali@xxxxxxxxxx Tested-by: Tomasz Maciej Nowak <tmn505@xxxxxxxxx> Signed-off-by: Pali Rohár <pali@xxxxxxxxxx> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> Reviewed-by: Rob Herring <robh@xxxxxxxxxx> Acked-by: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxx> Signed-off-by: Marek Behún <kabel@xxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/pci/host/pci-aardvark.c | 42 ++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 23 deletions(-) --- a/drivers/pci/host/pci-aardvark.c +++ b/drivers/pci/host/pci-aardvark.c @@ -29,17 +29,7 @@ #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) -#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 -#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) -#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 -#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) -#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 -#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 -#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 -#define PCIE_CORE_LINK_L0S_ENTRY BIT(0) -#define PCIE_CORE_LINK_TRAINING BIT(5) -#define PCIE_CORE_LINK_SPEED_SHIFT 16 -#define PCIE_CORE_LINK_WIDTH_SHIFT 20 +#define PCIE_CORE_PCIEXP_CAP 0xc0 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) @@ -229,6 +219,11 @@ static inline u32 advk_readl(struct advk return readl(pcie->base + reg); } +static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg) +{ + return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8); +} + static int advk_pcie_link_up(struct advk_pcie *pcie) { u32 val, ltssm_state; @@ -301,16 +296,16 @@ static int advk_pcie_train_at_gen(struct * Start link training immediately after enabling it. * This solves problems for some buggy cards. */ - reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); - reg |= PCIE_CORE_LINK_TRAINING; - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); + reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); + reg |= PCI_EXP_LNKCTL_RL; + advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); ret = advk_pcie_wait_for_link(pcie); if (ret) return ret; - reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); - neg_gen = (reg >> PCIE_CORE_LINK_SPEED_SHIFT) & 0xf; + reg = advk_read16(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKSTA); + neg_gen = reg & PCI_EXP_LNKSTA_CLS; return neg_gen; } @@ -400,13 +395,14 @@ static void advk_pcie_setup_hw(struct ad PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); - /* Set PCIe Device Control and Status 1 PF0 register */ - reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | - (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | - PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | - (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << - PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); - advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); + /* Set PCIe Device Control register */ + reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); + reg &= ~PCI_EXP_DEVCTL_RELAX_EN; + reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; + reg &= ~PCI_EXP_DEVCTL_READRQ; + reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */ + reg |= PCI_EXP_DEVCTL_READRQ_512B; + advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); /* Program PCIe Control 2 to disable strict ordering */ reg = PCIE_CORE_CTRL2_RESERVED | Patches currently in stable-queue which might be from kabel@xxxxxxxxxx are queue-4.14/pci-aardvark-move-pcie-reset-card-code-to-advk_pcie_train_link.patch queue-4.14/pci-aardvark-introduce-an-advk_pcie_valid_device-helper.patch queue-4.14/pci-aardvark-update-comment-about-disabling-link-training.patch queue-4.14/pci-aardvark-train-link-immediately-after-enabling-training.patch queue-4.14/arm64-dts-marvell-armada-37xx-declare-pcie-reset-pin.patch queue-4.14/pci-aardvark-replace-custom-macros-by-standard-linux-pci_regs.h-macros.patch queue-4.14/pci-aardvark-fix-a-leaked-reference-by-adding-missing-of_node_put.patch queue-4.14/pci-aardvark-fix-pcie-max-payload-size-setting.patch queue-4.14/pinctrl-armada-37xx-correct-pwm-pins-definitions.patch queue-4.14/arm64-dts-marvell-armada-37xx-set-pcie_reset_pin-to-gpio-function.patch queue-4.14/pci-aardvark-configure-pcie-resources-from-ranges-dt-property.patch queue-4.14/pci-aardvark-improve-link-training.patch queue-4.14/pci-aardvark-fix-link-training.patch queue-4.14/pci-aardvark-fix-checking-for-link-up-via-ltssm-state.patch queue-4.14/pci-aardvark-issue-perst-via-gpio.patch queue-4.14/pinctrl-armada-37xx-correct-mpp-definitions.patch queue-4.14/pci-add-pci_exp_lnkctl2_tls-macros.patch queue-4.14/pci-aardvark-wait-for-endpoint-to-be-ready-before-training-link.patch queue-4.14/pinctrl-armada-37xx-add-missing-pin-pcie1-wakeup.patch queue-4.14/pci-aardvark-fix-compilation-on-s390.patch queue-4.14/pci-aardvark-fix-i-o-space-page-leak.patch queue-4.14/pci-aardvark-don-t-touch-pcie-registers-if-no-card-connected.patch queue-4.14/pci-aardvark-remove-pcie-outbound-window-configuration.patch queue-4.14/pci-aardvark-indicate-error-in-val-when-config-read-fails.patch