Patch "clk: at91: clk-master: check if div or pres is zero" has been added to the 5.14-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: at91: clk-master: check if div or pres is zero

to the 5.14-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-at91-clk-master-check-if-div-or-pres-is-zero.patch
and it can be found in the queue-5.14 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit f1cb422ca8efa5cba80c80376d0799a851799632
Author: Claudiu Beznea <claudiu.beznea@xxxxxxxxxxxxx>
Date:   Mon Oct 11 14:27:12 2021 +0300

    clk: at91: clk-master: check if div or pres is zero
    
    [ Upstream commit c2910c00fee4cbb7b222d6e02846adef9ae4135a ]
    
    Check if div or pres is zero before using it as argument for ffs().
    In case div is zero ffs() will return 0 and thus substracting from
    zero will lead to invalid values to be setup in registers.
    
    Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
    Fixes: 75c88143f3b87 ("clk: at91: clk-master: add master clock support for SAMA7G5")
    Signed-off-by: Claudiu Beznea <claudiu.beznea@xxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@xxxxxxxxxxxxx
    Acked-by: Nicolas Ferre <nicolas.ferre@xxxxxxxxxxxxx>
    Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index a80427980bf73..2e410815a3405 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -280,7 +280,7 @@ static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	else if (pres == 3)
 		pres = MASTER_PRES_MAX;
-	else
+	else if (pres)
 		pres = ffs(pres) - 1;
 
 	spin_lock_irqsave(master->lock, flags);
@@ -610,7 +610,7 @@ static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	if (div == 3)
 		div = MASTER_PRES_MAX;
-	else
+	else if (div)
 		div = ffs(div) - 1;
 
 	spin_lock_irqsave(master->lock, flags);



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