Patch "MIPS: lantiq: dma: fix burst length for DEU" has been added to the 5.14-stable tree

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This is a note to let you know that I've just added the patch titled

    MIPS: lantiq: dma: fix burst length for DEU

to the 5.14-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     mips-lantiq-dma-fix-burst-length-for-deu.patch
and it can be found in the queue-5.14 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 73ea6dc23b6a54eb5da2f2bf87c3cad70a5f41ce
Author: Aleksander Jan Bajkowski <olek2@xxxxx>
Date:   Tue Sep 14 23:21:00 2021 +0200

    MIPS: lantiq: dma: fix burst length for DEU
    
    [ Upstream commit 5ad74d39c51dd41b3c819f4f5396655f0629b4fd ]
    
    The current definition of 2W burst length is invalid.
    This patch fixes it. Current downstream DEU driver doesn't
    use DMA. An incorrect burst length value doesn't cause any
    errors. This patch also adds other burst length values.
    
    Fixes: dfec1a827d2b ("MIPS: Lantiq: Add DMA support")
    Signed-off-by: Aleksander Jan Bajkowski <olek2@xxxxx>
    Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 364ab39eb8a41..53fcc672a2944 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -41,7 +41,11 @@
 #define DMA_IRQ_ACK		0x7e		/* IRQ status register */
 #define DMA_POLL		BIT(31)		/* turn on channel polling */
 #define DMA_CLK_DIV4		BIT(6)		/* polling clock divider */
-#define DMA_2W_BURST		BIT(1)		/* 2 word burst length */
+#define DMA_PCTRL_2W_BURST	0x1		/* 2 word burst length */
+#define DMA_PCTRL_4W_BURST	0x2		/* 4 word burst length */
+#define DMA_PCTRL_8W_BURST	0x3		/* 8 word burst length */
+#define DMA_TX_BURST_SHIFT	4		/* tx burst shift */
+#define DMA_RX_BURST_SHIFT	2		/* rx burst shift */
 #define DMA_ETOP_ENDIANNESS	(0xf << 8) /* endianness swap etop channels */
 #define DMA_WEIGHT	(BIT(17) | BIT(16))	/* default channel wheight */
 
@@ -192,7 +196,8 @@ ltq_dma_init_port(int p)
 		break;
 
 	case DMA_PORT_DEU:
-		ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
+		ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
+			(DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
 			LTQ_DMA_PCTRL);
 		break;
 



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