Patch "arm64: dts: qcom: sc7280: fix display port phy reg property" has been added to the 5.15-stable tree

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This is a note to let you know that I've just added the patch titled

    arm64: dts: qcom: sc7280: fix display port phy reg property

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-dts-qcom-sc7280-fix-display-port-phy-reg-prope.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit e0c4be58a79ae29061a5fabe3aefa815944df07c
Author: Kuogee Hsieh <khsieh@xxxxxxxxxxxxxx>
Date:   Thu Sep 9 12:49:58 2021 -0700

    arm64: dts: qcom: sc7280: fix display port phy reg property
    
    [ Upstream commit 425f30cc843c727bc7753a0d33710d1e4a999168 ]
    
    Existing display port phy reg property is derived from usb phy which
    map display port phy pcs to wrong address which cause aux init
    with wrong address and prevent both dpcd read and write from working.
    Fix this problem by assigning correct pcs address to display port
    phy reg property.
    
    Fixes: bb9efa59c665 ("arm64: dts: qcom: sc7280: Add USB related nodes")
    Signed-off-by: Kuogee Hsieh <khsieh@xxxxxxxxxxxxxx>
    Reviewed-by: Stephen Boyd <swboyd@xxxxxxxxxxxx>
    Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/1631216998-10049-1-git-send-email-khsieh@xxxxxxxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fd78f16181ddd..f58336536a92a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1258,15 +1258,11 @@
 			dp_phy: dp-phy@88ea200 {
 				reg = <0 0x088ea200 0 0x200>,
 				      <0 0x088ea400 0 0x200>,
-				      <0 0x088eac00 0 0x400>,
+				      <0 0x088eaa00 0 0x200>,
 				      <0 0x088ea600 0 0x200>,
-				      <0 0x088ea800 0 0x200>,
-				      <0 0x088eaa00 0 0x100>;
+				      <0 0x088ea800 0 0x200>;
 				#phy-cells = <0>;
 				#clock-cells = <1>;
-				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
-				clock-names = "pipe0";
-				clock-output-names = "usb3_phy_pipe_clk_src";
 			};
 		};
 



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